Refactor PUSH/POP in ARM assemblers.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 185 matching lines @@
   OpEncodingMemEx
 };
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   int32_t Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }
 
 IValueT getEncodedSRegNum(const Variable *Var) {
-  assert(Var->hasReg());
   assert(RegARM32::isEncodedSReg(Var->getRegNum()));
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
 // The way an operand is encoded into a sequence of bits in functions
 // encodeOperand and encodeAddress below.
 enum EncodedOperand {
   // Unable to encode, value left undefined.
   CantEncode = 0,
   // Value is register found.
@@ skipping 1464 matching lines @@
   //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
   //
   // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr const char *OrrName = "orr";
   constexpr IValueT OrrOpcode = B3 | B2; // i.e. 1100
   emitType01(Cond, OrrOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              OrrName);
 }
 
-void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
+void AssemblerARM32::pop(const Variable *OpRt, CondARM32::Cond Cond) {
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Pop = "pop";
-  IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
+  const IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Pop);
   // Same as load instruction.
   constexpr bool IsLoad = true;
   constexpr bool IsByte = false;
   IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
                                        OperandARM32Mem::PostIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address, Pop);
 }
 
 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) {
@@ skipping 294 matching lines @@
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs, const char *InstName) {
-
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
   assert(0 < NumConsecRegs);
   (void)VpushVpopMaxConsecRegs;
   assert(NumConsecRegs <= VpushVpopMaxConsecRegs);
   assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
   verifyCondDefined(Cond, InstName);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
@@ skipping 28 matching lines @@
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr const char *VpushName = "vpush";
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice