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Unified Diff: src/mips64/disasm-mips64.cc

Issue 1534183002: MIPS64: r6 compact branch optimization. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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« src/mips64/constants-mips64.cc ('K') | « src/mips64/constants-mips64.cc ('k') | src/mips64/macro-assembler-mips64.h » ('j') | src/mips64/simulator-mips64.h » ('J')
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Index: src/mips64/disasm-mips64.cc
diff --git a/src/mips64/disasm-mips64.cc b/src/mips64/disasm-mips64.cc
index 192f6cf8ee434de48dc3572857d1e47f22b93318..39b4732f822b100246c87ab207c2d70c5ea369c9 100644
--- a/src/mips64/disasm-mips64.cc
+++ b/src/mips64/disasm-mips64.cc
@@ -91,7 +91,7 @@ class Decoder {
void PrintXImm19(Instruction* instr);
void PrintSImm19(Instruction* instr);
void PrintXImm21(Instruction* instr);
-
+ void PrintSImm21(Instruction* instr);
void PrintPCImm21(Instruction* instr, int delta_pc, int n_bits);
void PrintXImm26(Instruction* instr);
void PrintSImm26(Instruction* instr);
@@ -337,6 +337,16 @@ void Decoder::PrintXImm21(Instruction* instr) {
}
+// Print 21-bit signed immediate value.
+void Decoder::PrintSImm21(Instruction* instr) {
+ int32_t imm21 = instr->Imm21Value();
+ // set sign
+ imm21 <<= (32 - kImm21Bits);
+ imm21 >>= (32 - kImm21Bits);
+ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
+}
+
+
// Print absoulte address for 21-bit offset or immediate value.
// The absolute address is calculated according following expression:
// PC + delta_pc + (offset << n_bits)
@@ -614,6 +624,10 @@ int Decoder::FormatOption(Instruction* instr, const char* format) {
} else if (format[3] == '2' && format[4] == '1') {
DCHECK(STRING_STARTS_WITH(format, "imm21"));
switch (format[5]) {
+ case 's':
+ DCHECK(STRING_STARTS_WITH(format, "imm21s"));
+ PrintSImm21(instr);
+ break;
case 'x':
DCHECK(STRING_STARTS_WITH(format, "imm21x"));
PrintXImm21(instr);
@@ -1605,12 +1619,12 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
Format(instr, "blez 'rs, 'imm16u -> 'imm16p4s2");
} else if ((instr->RtValue() != instr->RsValue()) &&
(instr->RsValue() != 0) && (instr->RtValue() != 0)) {
- Format(instr, "bgeuc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
+ Format(instr, "bgeuc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
} else if ((instr->RtValue() == instr->RsValue()) &&
(instr->RtValue() != 0)) {
- Format(instr, "bgezalc 'rs, 'imm16u -> 'imm16p4s2");
+ Format(instr, "bgezalc 'rs, 'imm16u -> 'imm16p4s2");
} else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
- Format(instr, "blezalc 'rt, 'imm16u -> 'imm16p4s2");
+ Format(instr, "blezalc 'rt, 'imm16u -> 'imm16p4s2");
} else {
UNREACHABLE();
}
@@ -1647,7 +1661,7 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
Format(instr, "bltzc 'rt, 'imm16u -> 'imm16p4s2");
} else if ((instr->RtValue() != instr->RsValue()) &&
(instr->RsValue() != 0) && (instr->RtValue() != 0)) {
- Format(instr, "bltc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
+ Format(instr, "bltc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
} else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
Format(instr, "bgtzc 'rt, 'imm16u -> 'imm16p4s2");
} else {
@@ -1658,14 +1672,14 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
if (instr->RsValue() == JIC) {
Format(instr, "jic 'rt, 'imm16s");
} else {
- Format(instr, "beqzc 'rs, 'imm21x -> 'imm21p4s2");
+ Format(instr, "beqzc 'rs, 'imm21s -> 'imm21p4s2");
}
break;
case POP76:
if (instr->RsValue() == JIALC) {
- Format(instr, "jialc 'rt, 'imm16x");
+ Format(instr, "jialc 'rt, 'imm16s");
} else {
- Format(instr, "bnezc 'rs, 'imm21x -> 'imm21p4s2");
+ Format(instr, "bnezc 'rs, 'imm21s -> 'imm21p4s2");
}
break;
// ------------- Arithmetic instructions.
@@ -1673,13 +1687,17 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
if (kArchVariant != kMips64r6) {
Format(instr, "addi 'rt, 'rs, 'imm16s");
} else {
- // Check if BOVC or BEQC instruction.
- if (instr->RsValue() >= instr->RtValue()) {
+ int rs_reg = instr->RsValue();
+ int rt_reg = instr->RtValue();
+ // Check if BOVC, BEQZALC or BEQC instruction.
+ if (rs_reg >= rt_reg) {
Format(instr, "bovc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
- } else if (instr->RsValue() < instr->RtValue()) {
- Format(instr, "beqc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
} else {
Ilija.Pavlovic1 2015/12/18 11:38:22 One of conditions is (rt_reg != 0): if (rt_reg !=
balazs.kilvady 2015/12/18 19:18:05 One more thing to backport...
ivica.bogosavljevic 2015/12/22 10:22:40 I'll add DCHECK(rt_reg > 0) before if (rs_reg == 0
ivica.bogosavljevic 2015/12/22 10:22:40 Acknowledged.
- UNREACHABLE();
+ if (rs_reg == 0) {
+ Format(instr, "beqzalc 'rt, 'imm16s -> 'imm16p4s2");
+ } else {
+ Format(instr, "beqc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
+ }
}
}
break;
@@ -1687,13 +1705,17 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
if (kArchVariant != kMips64r6) {
Format(instr, "daddi 'rt, 'rs, 'imm16s");
} else {
- // Check if BNVC or BNEC instruction.
- if (instr->RsValue() >= instr->RtValue()) {
+ int rs_reg = instr->RsValue();
+ int rt_reg = instr->RtValue();
+ // Check if BNVC, BNEZALC or BNEC instruction.
+ if (rs_reg >= rt_reg) {
Format(instr, "bnvc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
- } else if (instr->RsValue() < instr->RtValue()) {
- Format(instr, "bnec 'rs, 'rt, 'imm16s -> 'imm16p4s2");
} else {
Ilija.Pavlovic1 2015/12/18 11:38:22 One of conditions is (rt_reg != 0): if (rt_reg !=
ivica.bogosavljevic 2015/12/22 10:22:40 I'll add DCHECK(rt_reg > 0) before if (rs_reg == 0
- UNREACHABLE();
+ if (rs_reg == 0) {
+ Format(instr, "bnezalc 'rt, 'imm16s -> 'imm16p4s2");
+ } else {
+ Format(instr, "bnec 'rs, 'rt, 'imm16s -> 'imm16p4s2");
+ }
}
}
break;
« src/mips64/constants-mips64.cc ('K') | « src/mips64/constants-mips64.cc ('k') | src/mips64/macro-assembler-mips64.h » ('j') | src/mips64/simulator-mips64.h » ('J')

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