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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #if V8_TARGET_ARCH_MIPS64 | 5 #if V8_TARGET_ARCH_MIPS64 |
6 | 6 |
7 #include "src/mips64/constants-mips64.h" | 7 #include "src/mips64/constants-mips64.h" |
8 | 8 |
9 namespace v8 { | 9 namespace v8 { |
10 namespace internal { | 10 namespace internal { |
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119 } | 119 } |
120 | 120 |
121 // No Cregister with the reguested name found. | 121 // No Cregister with the reguested name found. |
122 return kInvalidFPURegister; | 122 return kInvalidFPURegister; |
123 } | 123 } |
124 | 124 |
125 | 125 |
126 // ----------------------------------------------------------------------------- | 126 // ----------------------------------------------------------------------------- |
127 // Instructions. | 127 // Instructions. |
128 | 128 |
129 bool Instruction::IsForbiddenInBranchDelay() const { | 129 bool Instruction::IsForbiddenAfterBranchInstr(Instr instr) { |
130 const int op = OpcodeFieldRaw(); | 130 Opcode opcode = static_cast<Opcode>(instr & kOpcodeMask); |
131 switch (op) { | 131 switch (opcode) { |
132 case J: | 132 case J: |
133 case JAL: | 133 case JAL: |
134 case BEQ: | 134 case BEQ: |
135 case BNE: | 135 case BNE: |
136 case BLEZ: | 136 case BLEZ: // POP06 bgeuc/bleuc, blezalc, bgezalc |
137 case BGTZ: | 137 case BGTZ: // POP07 bltuc/bgtuc, bgtzalc, bltzalc |
138 case BEQL: | 138 case BEQL: |
139 case BNEL: | 139 case BNEL: |
140 case BLEZL: | 140 case BLEZL: // POP26 bgezc, blezc, bgec/blec |
141 case BGTZL: | 141 case BGTZL: // POP27 bgtzc, bltzc, bltc/bgtc |
142 case BC: | 142 case BC: |
143 case BALC: | 143 case BALC: |
| 144 case POP10: // beqzalc, bovc, beqc |
| 145 case POP30: // bnezalc, bnvc, bnec |
| 146 case POP66: // beqzc, jic |
| 147 case POP76: // bnezc, jialc |
144 return true; | 148 return true; |
145 case REGIMM: | 149 case REGIMM: |
146 switch (RtFieldRaw()) { | 150 switch (instr & kRtFieldMask) { |
147 case BLTZ: | 151 case BLTZ: |
148 case BGEZ: | 152 case BGEZ: |
149 case BLTZAL: | 153 case BLTZAL: |
150 case BGEZAL: | 154 case BGEZAL: |
151 return true; | 155 return true; |
152 default: | 156 default: |
153 return false; | 157 return false; |
154 } | 158 } |
155 break; | 159 break; |
156 case SPECIAL: | 160 case SPECIAL: |
157 switch (FunctionFieldRaw()) { | 161 switch (instr & kFunctionFieldMask) { |
158 case JR: | 162 case JR: |
159 case JALR: | 163 case JALR: |
160 return true; | 164 return true; |
161 default: | 165 default: |
162 return false; | 166 return false; |
163 } | 167 } |
164 break; | 168 break; |
| 169 case COP1: |
| 170 switch (instr & kRsFieldMask) { |
| 171 case BC1: |
| 172 case BC1EQZ: |
| 173 case BC1NEZ: |
| 174 return true; |
| 175 break; |
| 176 default: |
| 177 return false; |
| 178 } |
| 179 break; |
165 default: | 180 default: |
166 return false; | 181 return false; |
167 } | 182 } |
168 } | 183 } |
169 | 184 |
170 | 185 |
171 bool Instruction::IsLinkingInstruction() const { | 186 bool Instruction::IsLinkingInstruction() const { |
172 const int op = OpcodeFieldRaw(); | 187 switch (OpcodeFieldRaw()) { |
173 switch (op) { | |
174 case JAL: | 188 case JAL: |
175 return true; | 189 return true; |
176 case POP76: | 190 case POP76: |
177 if (RsFieldRawNoAssert() == JIALC) | 191 if (RsFieldRawNoAssert() == JIALC) |
178 return true; // JIALC | 192 return true; // JIALC |
179 else | 193 else |
180 return false; // BNEZC | 194 return false; // BNEZC |
181 case REGIMM: | 195 case REGIMM: |
182 switch (RtFieldRaw()) { | 196 switch (RtFieldRaw()) { |
183 case BGEZAL: | 197 case BGEZAL: |
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216 return false; | 230 return false; |
217 } | 231 } |
218 } | 232 } |
219 } | 233 } |
220 | 234 |
221 | 235 |
222 } // namespace internal | 236 } // namespace internal |
223 } // namespace v8 | 237 } // namespace v8 |
224 | 238 |
225 #endif // V8_TARGET_ARCH_MIPS64 | 239 #endif // V8_TARGET_ARCH_MIPS64 |
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