MIPS64: r6 compact branch optimization.

src/compiler/mips64/code-generator-mips64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/ast/scopes.h"
 #include "src/compiler/code-generator.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/osr.h"
@@ skipping 1535 matching lines @@
     __ li(at, Operand(i.InputInt32(index + 0)));
     __ beq(input, at, GetLabel(i.InputRpo(index + 1)));
   }
   __ nop();  // Branch delay slot of the last beq.
   AssembleArchJump(i.InputRpo(1));
 }
 
 
 void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
   MipsOperandConverter i(this, instr);
   Register input = i.InputRegister(0);

[ivica.bogosavljevic, 2015/12/18 08:56:32]

Patch tested on MIPS64 R2 and R6, simulator and qemu-userland and no regressions
found

[ivica.bogosavljevic, 2015/12/22 10:22:39]

Patch also tested on MIPS64R6 Big-Endian under qemu-userland and no regressions
found

   size_t const case_count = instr->InputCount() - 2;
   Label here;
 
   __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
   __ BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 + 7);
   // Ensure that dd-ed labels use 8 byte aligned addresses.
-  if ((masm()->pc_offset() & 7) != 0) {
-    __ nop();
-  }
+  __ Align(8);
   __ bal(&here);
   __ dsll(at, input, 3);  // Branch delay slot.
   __ bind(&here);
   __ daddu(at, at, ra);
   __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
   __ jr(at);
   __ nop();  // Branch delay slot nop.
   for (size_t index = 0; index < case_count; ++index) {
     __ dd(GetLabel(i.InputRpo(index + 2)));
   }
@@ skipping 310 matching lines @@
       padding_size -= v8::internal::Assembler::kInstrSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8