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Side by Side Diff: src/IceAssemblerARM32.cpp

Issue 1534133003: Fix minimal build for constant VpushVpopMaxConsecRegs. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years ago
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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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2007 } 2007 }
2008 2008
2009 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode, 2009 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
2010 const Variable *OpBaseReg, 2010 const Variable *OpBaseReg,
2011 SizeT NumConsecRegs, const char *InstName) { 2011 SizeT NumConsecRegs, const char *InstName) {
2012 2012
2013 const IValueT BaseReg = getEncodedSRegNum(OpBaseReg); 2013 const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
2014 const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register. 2014 const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
2015 const IValueT Rd = mask(BaseReg, 1, 4); // Top 4 bits of base register. 2015 const IValueT Rd = mask(BaseReg, 1, 4); // Top 4 bits of base register.
2016 assert(0 < NumConsecRegs); 2016 assert(0 < NumConsecRegs);
2017 (void)VpushVpopMaxConsecRegs;
2017 assert(NumConsecRegs <= VpushVpopMaxConsecRegs); 2018 assert(NumConsecRegs <= VpushVpopMaxConsecRegs);
2018 assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs()); 2019 assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
2019 verifyCondDefined(Cond, InstName); 2020 verifyCondDefined(Cond, InstName);
2020 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 2021 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
2021 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit | 2022 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
2022 (Rd << kRdShift) | NumConsecRegs; 2023 (Rd << kRdShift) | NumConsecRegs;
2023 emitInst(Encoding); 2024 emitInst(Encoding);
2024 } 2025 }
2025 2026
2026 void AssemblerARM32::vpop(const Variable *OpBaseReg, SizeT NumConsecRegs, 2027 void AssemblerARM32::vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
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2050 // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and 2051 // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
2051 // iiiiiiii=NumConsecRegs. 2052 // iiiiiiii=NumConsecRegs.
2052 constexpr const char *VpushName = "vpush"; 2053 constexpr const char *VpushName = "vpush";
2053 constexpr IValueT VpushOpcode = 2054 constexpr IValueT VpushOpcode =
2054 B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9; 2055 B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
2055 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName); 2056 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName);
2056 } 2057 }
2057 2058
2058 } // end of namespace ARM32 2059 } // end of namespace ARM32
2059 } // end of namespace Ice 2060 } // end of namespace Ice
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