Add VPUSH/VPOP instructions to the ARM32 integrated assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the InstARM32 and OperandARM32 classes, primarily the
 /// constructors and the dump()/emit() methods.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceInstARM32.h"
 
 #include "IceAssemblerARM32.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceInst.h"
 #include "IceOperand.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLoweringARM32.h"
 
 namespace Ice {
 
 namespace {
 
+// maximum number of registers allowed in vpush/vpop.
+static constexpr SizeT VpushVpopMaxConsecRegs = 16;
+
 const struct TypeARM32Attributes_ {
   const char *WidthString;    // b, h, <blank>, or d
   const char *VecWidthString; // i8, i16, i32, f32, f64
   int8_t SExtAddrOffsetBits;
   int8_t ZExtAddrOffsetBits;
 } TypeARM32Attributes[] = {
 #define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)  \
   { int_width, vec_width, sbits, ubits }                                       \
   ,
     ICETYPEARM32_TABLE
@@ skipping 1248 matching lines @@
 template <> void InstARM32Uxt::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->uxt(getDest(), getSrc(0), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 namespace {
 
-bool isAssignedConsecutiveRegisters(Variable *Before, Variable *After) {
+bool isAssignedConsecutiveRegisters(const Variable *Before,
+                                    const Variable *After) {
   assert(Before->hasReg());
   assert(After->hasReg());
   return Before->getRegNum() + 1 == After->getRegNum();
 }
 
 } // end of anonymous namespace
 
 void InstARM32Pop::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 48 matching lines @@
   }
   Dests[Start]->emit(Func);
   for (SizeT j = Start + 1; j <= End; ++j) {
     Str << ", ";
     Dests[j]->emit(Func);
   }
   Str << "}";
 }
 
 void InstARM32Pop::emitIAS(const Cfg *Func) const {
-  SizeT IntegerCount = 0;
-  ARM32::IValueT GPRegisters = 0;
-  const Variable *LastDest = nullptr;
-  for (const Variable *Var : Dests) {
-    if (!isScalarIntegerType(Var->getType()))
-      // TODO(kschimpf) Implement vpush.
-      return emitUsingTextFixup(Func);
-    assert((Var && Var->hasReg()) && "pop only applies to registers");
-    int32_t Reg = Var->getRegNum();
-    assert(Reg != RegARM32::Encoded_Not_GPR);
-    LastDest = Var;
-    GPRegisters |= (1 << Reg);
-    ++IntegerCount;
+  // Pop can't be emitted if there are no registers to load. This should never
+  // happen, but if it does, we don't need to bring Subzero down -- we just skip
+  // emitting the pop instruction (and maybe emit a nop?) The assert() is here
+  // so that we can detect this error during development.
+  const SizeT DestSize = Dests.size();
+  if (DestSize == 0) {
+    assert(false && "Empty pop list");
+    return;
   }
+
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
-  switch (IntegerCount) {
-  case 0:
-    return;
-  case 1:
-    // Note: Can only apply pop register if single register is not sp.
-    assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) &&
-           "Effects of pop register SP is undefined!");
-    Asm->pop(LastDest, CondARM32::AL);
-    break;
-  default:
-    Asm->popList(GPRegisters, CondARM32::AL);
-    break;
+  const auto *Reg = llvm::cast<Variable>(Dests[0]);
+  if (isScalarIntegerType(Reg->getType())) {
+    // Pop GPR registers.
+    SizeT IntegerCount = 0;
+    ARM32::IValueT GPRegisters = 0;
+    const Variable *LastDest = nullptr;
+    for (const Variable *Var : Dests) {
+      assert((Var && Var->hasReg()) && "pop only applies to registers");

[Jim Stichnoth, 2015/12/18 00:03:11]

I think you can assume Var!=nullptr, and remove that test from the assert?

[Karl, 2015/12/18 16:26:50]

Done.

+      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      LastDest = Var;
+      GPRegisters |= (1 << Reg);
+      ++IntegerCount;
+    }
+    switch (IntegerCount) {
+    case 0:
+      return;
+    case 1:
+      // Note: Can only apply pop register if single register is not sp.
+      assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) &&
+             "Effects of pop register SP is undefined!");
+      Asm->pop(LastDest, CondARM32::AL);
+      break;
+    default:
+      Asm->popList(GPRegisters, CondARM32::AL);
+      break;
+    }
+  } else {
+    // Pop vector/floating point registers.
+    const Variable *BaseReg = nullptr;
+    SizeT RegCount = 0;
+    for (const Variable *NextReg : Dests) {
+      if (BaseReg == nullptr) {
+        BaseReg = NextReg;
+        RegCount = 1;
+      } else if (RegCount < VpushVpopMaxConsecRegs &&
+                 isAssignedConsecutiveRegisters(Reg, NextReg)) {
+        ++RegCount;
+      } else {
+        Asm->vpop(BaseReg, RegCount, CondARM32::AL);
+        BaseReg = NextReg;
+        RegCount = 1;
+      }
+      Reg = NextReg;
+    }
+    if (RegCount)
+      Asm->vpop(BaseReg, RegCount, CondARM32::AL);
   }
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 void InstARM32Pop::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "pop"
@@ skipping 14 matching lines @@
   // emitting the push instruction (and maybe emit a nop?) The assert() is here
   // so that we can detect this error during development.
   const SizeT SrcSize = getSrcSize();
   if (SrcSize == 0) {
     assert(false && "Empty push list");
     return;
   }
 
   Ostream &Str = Func->getContext()->getStrEmit();
 
-  auto *Reg = llvm::cast<Variable>(getSrc(0));
+  const auto *Reg = llvm::cast<Variable>(getSrc(0));
   if (isScalarIntegerType(Reg->getType())) {
     // GPR push.
     Str << "\t"
            "push"
            "\t{";
     Reg->emit(Func);
     for (SizeT i = 1; i < SrcSize; ++i) {
       Str << ", ";
       getSrc(i)->emit(Func);
     }
     Str << "}";
     return;
   }
 
   // VFP "s" reg push.
   Str << "\t"
          "vpush"
          "\t{";
   Reg->emit(Func);
+  SizeT RegCount = 1;
   for (SizeT i = 1; i < SrcSize; ++i) {
-    auto *NextReg = llvm::cast<Variable>(getSrc(i));
-    if (isAssignedConsecutiveRegisters(Reg, NextReg)) {
+    const auto *NextReg = llvm::cast<Variable>(getSrc(i));
+    if (RegCount < VpushVpopMaxConsecRegs &&
+        isAssignedConsecutiveRegisters(Reg, NextReg)) {
+      ++RegCount;
       Str << ", ";
     } else {
       startNextInst(Func);
+      RegCount = 1;
       Str << "}\n\t"
              "vpush"
              "\t{";
     }
     Reg = NextReg;
     Reg->emit(Func);
   }
   Str << "}";
 }
 
 void InstARM32Push::emitIAS(const Cfg *Func) const {
-  SizeT IntegerCount = 0;
-  ARM32::IValueT GPRegisters = 0;
-  const Variable *LastSrc = nullptr;
-  for (SizeT Index = 0; Index < getSrcSize(); ++Index) {
-    if (!isScalarIntegerType(getSrc(Index)->getType()))
-      // TODO(kschimpf) Implement vpush.
-      return emitUsingTextFixup(Func);
-    const auto *Var = llvm::dyn_cast<Variable>(getSrc(Index));
-    assert((Var && Var->hasReg()) && "push only applies to registers");
-    int32_t Reg = Var->getRegNum();
-    assert(Reg != RegARM32::Encoded_Not_GPR);
-    LastSrc = Var;
-    GPRegisters |= (1 << Reg);
-    ++IntegerCount;
+  // Push can't be emitted if there are no registers to save. This should never
+  // happen, but if it does, we don't need to bring Subzero down -- we just skip
+  // emitting the push instruction (and maybe emit a nop?) The assert() is here
+  // so that we can detect this error during development.
+  const SizeT SrcSize = getSrcSize();
+  if (SrcSize == 0) {
+    assert(false && "Empty push list");
+    return;
   }
+
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
-  switch (IntegerCount) {
-  case 0:
-    return;
-  case 1: {
-    // Note: Can only apply push register if single register is not sp.
-    assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) &&
-           "Effects of push register SP is undefined!");
-    Asm->push(LastSrc, CondARM32::AL);
-    break;
-  }
-  default:
-    // TODO(kschimpf) Implement pushList in assembler.
-    Asm->pushList(GPRegisters, CondARM32::AL);
-    break;
+  const auto *Reg = llvm::cast<Variable>(getSrc(0));
+  if (isScalarIntegerType(Reg->getType())) {
+    // Push GPR registers.
+    SizeT IntegerCount = 0;
+    ARM32::IValueT GPRegisters = 0;
+    const Variable *LastSrc = nullptr;
+    for (SizeT Index = 0; Index < getSrcSize(); ++Index) {
+      const auto *Var = llvm::cast<Variable>(getSrc(Index));
+      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      assert(Reg != RegARM32::Encoded_Not_GPR);
+      LastSrc = Var;
+      GPRegisters |= (1 << Reg);
+      ++IntegerCount;
+    }
+    switch (IntegerCount) {
+    case 0:
+      return;
+    case 1: {
+      // Note: Can only apply push register if single register is not sp.
+      assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) &&
+             "Effects of push register SP is undefined!");
+      Asm->push(LastSrc, CondARM32::AL);
+      break;
+    }
+    default:
+      Asm->pushList(GPRegisters, CondARM32::AL);
+      break;
+    }
+  } else {
+    // Push vector/Floating point registers.
+    const Variable *BaseReg = Reg;
+    SizeT RegCount = 1;
+    for (SizeT i = 1; i < SrcSize; ++i) {
+      const auto *NextReg = llvm::cast<Variable>(getSrc(i));
+      if (RegCount < VpushVpopMaxConsecRegs &&
+          isAssignedConsecutiveRegisters(Reg, NextReg)) {
+        ++RegCount;
+      } else {
+        Asm->vpush(BaseReg, RegCount, CondARM32::AL);
+        BaseReg = NextReg;
+        RegCount = 1;
+      }
+      Reg = NextReg;
+    }
+    Asm->vpush(BaseReg, RegCount, CondARM32::AL);
   }
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 void InstARM32Push::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "push"
@@ skipping 560 matching lines @@
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace Ice