Add VPUSH/VPOP instructions to the ARM32 integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 97 matching lines @@
 static constexpr IValueT kDivRmShift = 8;
 static constexpr IValueT kDivRnShift = 0;
 
 // Type of instruction encoding (bits 25-27). See ARM section A5.1
 static constexpr IValueT kInstTypeDataRegister = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataRegShift = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
 static constexpr IValueT kInstTypeMemImmediate = 2;  // i.e. 010
 static constexpr IValueT kInstTypeRegisterShift = 3; // i.e. 011
 
+// Limit on number of registers in a vpush/vpop.
+static constexpr SizeT VpushVpopMaxConsecRegs = 16;
+
 // Offset modifier to current PC for next instruction.  The offset is off by 8
 // due to the way the ARM CPUs read PC.
 static constexpr IOffsetT kPCReadOffset = 8;
 
 // Mask to pull out PC offset from branch (b) instruction.
 static constexpr int kBranchOffsetBits = 24;
 static constexpr IOffsetT kBranchOffsetMask = 0x00ffffff;
 
 IValueT encodeBool(bool B) { return B ? 1 : 0; }
 
@@ skipping 64 matching lines @@
   // actually expect a register.
   OpEncodingMemEx
 };
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   int32_t Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }
 
+IValueT getEncodedSRegNum(const Variable *Var) {
+  assert(Var->hasReg() && RegARM32::isEncodedSReg(Var->getRegNum()));

[Jim Stichnoth, 2015/12/18 00:03:11]

Better to change
  assert(c1 && c2);
into
  assert(c1);
  assert(c2);

[Karl, 2015/12/18 16:26:50]

Done.

+  return RegARM32::getEncodedSReg(Var->getRegNum());
+}
+
 // The way an operand is encoded into a sequence of bits in functions
 // encodeOperand and encodeAddress below.
 enum EncodedOperand {
   // Unable to encode, value left undefined.
   CantEncode = 0,
   // Value is register found.
   EncodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   EncodedAsRotatedImm8,
@@ skipping 1742 matching lines @@
   emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags, UmullName);
 }
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
+void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
+                                  const Variable *OpBaseReg,
+                                  SizeT NumConsecRegs, const char *InstName) {
+
+  IValueT BaseReg = getEncodedSRegNum(OpBaseReg);

[John, 2015/12/18 00:02:31]

Optional: const on everything that's a const

[Karl, 2015/12/18 16:26:50]

Done.

+  IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
+  IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
+  assert(0 < NumConsecRegs && NumConsecRegs <= VpushVpopMaxConsecRegs &&

[Jim Stichnoth, 2015/12/18 00:03:11]

Break this into 3 asserts, as above.

[Karl, 2015/12/18 16:26:50]

Done.

+         (BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
+  verifyCondDefined(Cond, InstName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
+                     (Rd << kRdShift) | NumConsecRegs;
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
+                          CondARM32::Cond Cond) {
+  // Note: Current implementation assumes that OpBaseReg is defined using S
+  // registers. It doesn't implement the D register form.
+  //
+  // VPOP - ARM section A8.8.367, encoding A2:
+  //  vpop<c> <RegList>
+  //
+  // cccc11001D111101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
+  // iiiiiiii=NumConsecRegs.
+  const char *VpopName = "vpop";

[Jim Stichnoth, 2015/12/18 00:03:10]

constexpr for these 2 vars

[Karl, 2015/12/18 16:26:50]

Done.

+  IValueT VpopOpcode = B27 | B26 | B23 | B21 | B20 | B19 | B18 | B16 | B11 | B9;
+  emitVStackOp(Cond, VpopOpcode, OpBaseReg, NumConsecRegs, VpopName);
+}
+
+void AssemblerARM32::vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
+                           CondARM32::Cond Cond) {
+  // Note: Current implementation assumes that OpBaseReg is defined using S
+  // registers. It doesn't implement the D register form.
+  //
+  // VPUSH - ARM section A8.8.368, encoding A2:
+  //   vpush<c> <RegList>
+  //
+  // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
+  // iiiiiiii=NumConsecRegs.
+  const char *VpushName = "vpush";

[Jim Stichnoth, 2015/12/18 00:03:11]

constexpr

[Karl, 2015/12/18 16:26:50]

Done.

+  IValueT VpushOpcode = B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
+  emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName);
+}
+
 } // end of namespace ARM32
 } // end of namespace Ice