Add option to force filetype=asm for testing

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 8e78228d709a248537a9426bbd56c325069e8896..e0c23149eb5803a25fb0c3acb9e863d115dcb935 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -219,7 +219,8 @@ void TargetX8632::lowerCall(const InstCall *Instr) {
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
-    switch (Dest->getType()) {
+    const Type DestTy = Dest->getType();
+    switch (DestTy) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Invalid Call dest type");
@@ -228,7 +229,8 @@ void TargetX8632::lowerCall(const InstCall *Instr) {
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
-      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax);
+      ReturnReg = makeReg(
+          DestTy, Traits::getGprForType(DestTy, Traits::RegisterSet::Reg_al));

[Jim Stichnoth, 2016/01/10 03:08:56]

I don't really like this Reg_al trick.

At the very least, leave a TODO to fix things.

Ideally, i1/i8/16 here would be a fatal error because it violates the PNaCl ABI.
 Consequently, helpers __Sz_bitcast_8xi1_i8() and __Sz_bitcast_16xi1_i16() would
be changed to return i32, and the bitcast lowering code would add a trunc after
the helper call to make the types work out.

[sehr, 2016/01/11 21:49:48]

Done.

       break;
     case IceType_i64:
       ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
@@ -246,7 +248,7 @@ void TargetX8632::lowerCall(const InstCall *Instr) {
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
-      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
+      ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_xmm0);
       break;
     }
   }
@@ -303,10 +305,11 @@ void TargetX8632::lowerCall(const InstCall *Instr) {
       _mov(DestLo, ReturnReg);
       _mov(DestHi, ReturnRegHi);
     } else {
-      assert(Dest->getType() == IceType_i32 || Dest->getType() == IceType_i16 ||
-             Dest->getType() == IceType_i8 || Dest->getType() == IceType_i1 ||
-             isVectorType(Dest->getType()));
-      if (isVectorType(Dest->getType())) {
+      const Type DestTy = Dest->getType();
+      assert(DestTy == IceType_i32 || DestTy == IceType_i16 ||
+             DestTy == IceType_i8 || DestTy == IceType_i1 ||
+             isVectorType(DestTy));
+      if (isVectorType(DestTy)) {
         _movp(Dest, ReturnReg);
       } else {
         _mov(Dest, ReturnReg);
@@ -352,20 +355,23 @@ void TargetX8632::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
+    const Type Src0Ty = Src0->getType();
     // TODO(jpp): this is not needed.
-    if (Src0->getType() == IceType_i64) {
+    if (Src0Ty == IceType_i64) {
       Variable *eax =
           legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax);
       Variable *edx =
           legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
       Reg = eax;
       Context.insert<InstFakeUse>(edx);
-    } else if (isScalarFloatingType(Src0->getType())) {
+    } else if (isScalarFloatingType(Src0Ty)) {
       _fld(Src0);
-    } else if (isVectorType(Src0->getType())) {
+    } else if (isVectorType(Src0Ty)) {
       Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
-      _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
+      assert(isScalarIntegerType(Src0Ty));
+      _mov(Reg, Src0,
+           Traits::getGprForType(Src0Ty, Traits::RegisterSet::Reg_eax));

[Jim Stichnoth, 2016/01/10 03:08:56]

Similar comment to above.  The lit tests that define functions with i1/i8/i16
return values are broken and ought to be fixed.

[sehr, 2016/01/11 21:49:48]

Done.

     }
   }
   // Add a ret instruction even if sandboxing is enabled, because addEpilog