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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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198 Variable *ReturnReg = nullptr; | 198 Variable *ReturnReg = nullptr; |
199 Variable *ReturnRegHi = nullptr; | 199 Variable *ReturnRegHi = nullptr; |
200 if (Dest) { | 200 if (Dest) { |
201 switch (Dest->getType()) { | 201 switch (Dest->getType()) { |
202 case IceType_NUM: | 202 case IceType_NUM: |
203 case IceType_void: | 203 case IceType_void: |
204 llvm::report_fatal_error("Invalid Call dest type"); | 204 llvm::report_fatal_error("Invalid Call dest type"); |
205 break; | 205 break; |
206 case IceType_i1: | 206 case IceType_i1: |
207 case IceType_i8: | 207 case IceType_i8: |
208 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_al); | |
209 break; | |
208 case IceType_i16: | 210 case IceType_i16: |
211 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_ax); | |
212 break; | |
209 case IceType_i32: | 213 case IceType_i32: |
210 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax); | 214 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax); |
Jim Stichnoth
2015/12/20 18:42:23
Instead of the above, I think you could do somethi
sehr
2016/01/07 18:53:11
Done.
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211 break; | 215 break; |
212 case IceType_i64: | 216 case IceType_i64: |
213 ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax); | 217 ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax); |
214 ReturnRegHi = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx); | 218 ReturnRegHi = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx); |
215 break; | 219 break; |
216 case IceType_f32: | 220 case IceType_f32: |
217 case IceType_f64: | 221 case IceType_f64: |
218 // Leave ReturnReg==ReturnRegHi==nullptr, and capture the result with the | 222 // Leave ReturnReg==ReturnRegHi==nullptr, and capture the result with the |
219 // fstp instruction. | 223 // fstp instruction. |
220 break; | 224 break; |
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335 Variable *eax = | 339 Variable *eax = |
336 legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax); | 340 legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax); |
337 Variable *edx = | 341 Variable *edx = |
338 legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx); | 342 legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx); |
339 Reg = eax; | 343 Reg = eax; |
340 Context.insert<InstFakeUse>(edx); | 344 Context.insert<InstFakeUse>(edx); |
341 } else if (isScalarFloatingType(Src0->getType())) { | 345 } else if (isScalarFloatingType(Src0->getType())) { |
342 _fld(Src0); | 346 _fld(Src0); |
343 } else if (isVectorType(Src0->getType())) { | 347 } else if (isVectorType(Src0->getType())) { |
344 Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0); | 348 Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0); |
349 } else if (Src0->getType() == IceType_i8) { | |
Jim Stichnoth
2015/12/20 18:42:23
Maybe check against i1 as well, for completeness
sehr
2016/01/07 18:53:11
I converted these all to use the getGprForType sch
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350 // TODO(sehr,stichnot): I think these need to sign/zero extend. | |
Jim Stichnoth
2015/12/20 18:42:23
I don't think the x86-32 processor ABI has anythin
sehr
2016/01/07 18:53:11
I'm going with the idea that we're doing this for
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351 _mov(Reg, Src0, Traits::RegisterSet::Reg_al); | |
352 } else if (Src0->getType() == IceType_i16) { | |
353 _mov(Reg, Src0, Traits::RegisterSet::Reg_ax); | |
345 } else { | 354 } else { |
346 _mov(Reg, Src0, Traits::RegisterSet::Reg_eax); | 355 _mov(Reg, Src0, Traits::RegisterSet::Reg_eax); |
347 } | 356 } |
348 } | 357 } |
349 // Add a ret instruction even if sandboxing is enabled, because addEpilog | 358 // Add a ret instruction even if sandboxing is enabled, because addEpilog |
350 // explicitly looks for a ret instruction as a marker for where to insert the | 359 // explicitly looks for a ret instruction as a marker for where to insert the |
351 // frame removal instructions. | 360 // frame removal instructions. |
352 _ret(Reg); | 361 _ret(Reg); |
353 // Add a fake use of esp to make sure esp stays alive for the entire | 362 // Add a fake use of esp to make sure esp stays alive for the entire |
354 // function. Otherwise post-call esp adjustments get dead-code eliminated. | 363 // function. Otherwise post-call esp adjustments get dead-code eliminated. |
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994 // case the high-level table has extra entries. | 1003 // case the high-level table has extra entries. |
995 #define X(tag, sizeLog2, align, elts, elty, str) \ | 1004 #define X(tag, sizeLog2, align, elts, elty, str) \ |
996 static_assert(_table1_##tag == _table2_##tag, \ | 1005 static_assert(_table1_##tag == _table2_##tag, \ |
997 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE"); | 1006 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE"); |
998 ICETYPE_TABLE | 1007 ICETYPE_TABLE |
999 #undef X | 1008 #undef X |
1000 } // end of namespace dummy3 | 1009 } // end of namespace dummy3 |
1001 } // end of anonymous namespace | 1010 } // end of anonymous namespace |
1002 | 1011 |
1003 } // end of namespace Ice | 1012 } // end of namespace Ice |
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