Add option to force filetype=asm for testing

tests_lit/assembler/x86/opcode_register_encodings.ll

 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like
 ; those for pmull vary more wildly depending on operand size (rather than
 ; follow a usual pattern).
 
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 -mattr=sse4.1 \
-; RUN:  -sandbox | FileCheck %s
+; RUN: %p2i --filetype=obj --disassemble --sandbox -i %s --args -O2 \
+; RUN:  -mattr=sse4.1 | FileCheck %s
 
 define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
 entry:
   %res = mul <8 x i16> %arg0, %arg1
   ret <8 x i16> %res
 ; CHECK-LABEL: test_mul_v8i16
 ; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1
 }
 
 ; Test register and address mode encoding.
@@ skipping 137 matching lines @@
   store i32 %v_add2, i32* %__8, align 1
 
   %z = add i32 %__6, 256
   %__9 = inttoptr i32 %z to i32*
   %v_add3 = add i32 %v, 91
   store i32 %v_add2, i32* %__9, align 1
 
   ret i32 %v
 }
 ; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: 65 8b 05 00 00 00 00  mov eax,DWORD PTR gs:0x0
+; CHECK: mov eax,{{(DWORD PTR )?}}gs:0x0
 ; CHECK: 8b 04 00              mov eax,DWORD PTR [eax+eax*1]
 ; CHECK: 65 8b 0d 00 00 00 00  mov ecx,DWORD PTR gs:0x0
 ; CHECK: 89 51 80              mov DWORD PTR [ecx-0x80],edx
 ; CHECK: 89 91 00 01 00 00     mov DWORD PTR [ecx+0x100],edx
 
 ; The 16-bit pinsrw/pextrw (SSE2) are quite different from
 ; the pinsr{b,d}/pextr{b,d} (SSE4.1).
 
 define internal <4 x i32> @test_pinsrd(<4 x i32> %vec, i32 %elt1, i32 %elt2,
                                        i32 %elt3, i32 %elt4) {
@@ skipping 123 matching lines @@
 three:
   %res3 = extractelement <8 x i16> %vec4, i32 7
   %res3_ext = zext i16 %res3 to i32
   ret i32 %res3_ext
 }
 ; CHECK-LABEL: test_pextrw
 ; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0
 ; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1
 ; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2
 ; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3