Add option to force filetype=asm for testing

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 201 matching lines @@
     // code eliminated as a result of the FakeKill of scratch registers after
     // the call.
     Context.insert<InstFakeUse>(Reg);
   }
   // Generate the call instruction. Assign its result to a temporary with high
   // register allocation weight.
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
-    switch (Dest->getType()) {
+    const Type DestTy = Dest->getType();
+    switch (DestTy) {
     case IceType_NUM:
     case IceType_void:
-      llvm::report_fatal_error("Invalid Call dest type");
-      break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
+      llvm::report_fatal_error("Invalid Call dest type");
+      break;
     case IceType_i32:
-      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax);
+      ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_eax);
       break;
     case IceType_i64:
       ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
       ReturnRegHi = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
       break;
     case IceType_f32:
     case IceType_f64:
       // Leave ReturnReg==ReturnRegHi==nullptr, and capture the result with the
       // fstp instruction.
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
-      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
+      ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_xmm0);
       break;
     }
   }
   Operand *CallTarget =
       legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs);
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     if (llvm::isa<Constant>(CallTarget)) {
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
     } else {
@@ skipping 36 matching lines @@
 
   // Assign the result of the call to Dest.
   if (ReturnReg) {
     if (ReturnRegHi) {
       auto *Dest64On32 = llvm::cast<Variable64On32>(Dest);
       Variable *DestLo = Dest64On32->getLo();
       Variable *DestHi = Dest64On32->getHi();
       _mov(DestLo, ReturnReg);
       _mov(DestHi, ReturnRegHi);
     } else {
-      assert(Dest->getType() == IceType_i32 || Dest->getType() == IceType_i16 ||
-             Dest->getType() == IceType_i8 || Dest->getType() == IceType_i1 ||
-             isVectorType(Dest->getType()));
-      if (isVectorType(Dest->getType())) {
+      const Type DestTy = Dest->getType();
+      assert(DestTy == IceType_i32 || DestTy == IceType_i16 ||
+             DestTy == IceType_i8 || DestTy == IceType_i1 ||
+             isVectorType(DestTy));
+      if (isVectorType(DestTy)) {
         _movp(Dest, ReturnReg);
       } else {
         _mov(Dest, ReturnReg);
       }
     }
   }
 }
 
 void TargetX8632::lowerArguments() {
   VarList &Args = Func->getArgs();
@@ skipping 25 matching lines @@
 
     Args[I] = RegisterArg;
     Context.insert<InstAssign>(Arg, RegisterArg);
   }
 }
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
+    const Type Src0Ty = Src0->getType();
     // TODO(jpp): this is not needed.
-    if (Src0->getType() == IceType_i64) {
+    if (Src0Ty == IceType_i64) {
       Variable *eax =
           legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax);
       Variable *edx =
           legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
       Reg = eax;
       Context.insert<InstFakeUse>(edx);
-    } else if (isScalarFloatingType(Src0->getType())) {
+    } else if (isScalarFloatingType(Src0Ty)) {
       _fld(Src0);
-    } else if (isVectorType(Src0->getType())) {
+    } else if (isVectorType(Src0Ty)) {
       Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
+      assert(Src0Ty == IceType_i32);
       _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because addEpilog
   // explicitly looks for a ret instruction as a marker for where to insert the
   // frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function. Otherwise post-call esp adjustments get dead-code eliminated.
   keepEspLiveAtExit();
@@ skipping 681 matching lines @@
 #define X(tag, sizeLog2, align, elts, elty, str)                               \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 } // end of anonymous namespace
 
 } // end of namespace X8632
 } // end of namespace Ice