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| 1 ;;===- subzero/runtime/szrt_ll.ll - Subzero runtime source ----------------===;; | 1 ;;===- subzero/runtime/szrt_ll.ll - Subzero runtime source ----------------===;; |
| 2 ;; | 2 ;; |
| 3 ;; The Subzero Code Generator | 3 ;; The Subzero Code Generator |
| 4 ;; | 4 ;; |
| 5 ;; This file is distributed under the University of Illinois Open Source | 5 ;; This file is distributed under the University of Illinois Open Source |
| 6 ;; License. See LICENSE.TXT for details. | 6 ;; License. See LICENSE.TXT for details. |
| 7 ;; | 7 ;; |
| 8 ;;===----------------------------------------------------------------------===;; | 8 ;;===----------------------------------------------------------------------===;; |
| 9 ;; | 9 ;; |
| 10 ;; This file implements wrappers for particular bitcode instructions that are | 10 ;; This file implements wrappers for particular bitcode instructions that are |
| 11 ;; too uncommon and complex for a particular target to bother implementing | 11 ;; too uncommon and complex for a particular target to bother implementing |
| 12 ;; directly in Subzero target lowering. This needs to be compiled by some | 12 ;; directly in Subzero target lowering. This needs to be compiled by some |
| 13 ;; non-Subzero compiler. | 13 ;; non-Subzero compiler. |
| 14 ;; | 14 ;; |
| 15 ;;===----------------------------------------------------------------------===;; | 15 ;;===----------------------------------------------------------------------===;; |
| 16 | 16 |
| 17 define <4 x float> @__Sz_uitofp_4xi32_4xf32(<4 x i32> %a) { | 17 define <4 x float> @__Sz_uitofp_4xi32_4xf32(<4 x i32> %a) { |
| 18 entry: | 18 entry: |
| 19 %0 = uitofp <4 x i32> %a to <4 x float> | 19 %0 = uitofp <4 x i32> %a to <4 x float> |
| 20 ret <4 x float> %0 | 20 ret <4 x float> %0 |
| 21 } | 21 } |
| 22 | 22 |
| 23 define <4 x i32> @__Sz_fptoui_4xi32_f32(<4 x float> %a) { | 23 define <4 x i32> @__Sz_fptoui_4xi32_f32(<4 x float> %a) { |
| 24 entry: | 24 entry: |
| 25 %0 = fptoui <4 x float> %a to <4 x i32> | 25 %0 = fptoui <4 x float> %a to <4 x i32> |
| 26 ret <4 x i32> %0 | 26 ret <4 x i32> %0 |
| 27 } | 27 } |
| 28 | 28 |
| 29 define i8 @__Sz_bitcast_8xi1_i8(<8 x i1> %a) { | 29 define i32 @__Sz_bitcast_8xi1_i8(<8 x i1> %a) { |
| 30 entry: | 30 entry: |
| 31 %0 = bitcast <8 x i1> %a to i8 | 31 %0 = bitcast <8 x i1> %a to i8 |
| 32 ret i8 %0 | 32 %ret = zext i8 %0 to i32 |
| 33 ret i32 %ret |
| 33 } | 34 } |
| 34 | 35 |
| 35 define i16 @__Sz_bitcast_16xi1_i16(<16 x i1> %a) { | 36 define i32 @__Sz_bitcast_16xi1_i16(<16 x i1> %a) { |
| 36 entry: | 37 entry: |
| 37 %0 = bitcast <16 x i1> %a to i16 | 38 %0 = bitcast <16 x i1> %a to i16 |
| 38 ret i16 %0 | 39 %ret = zext i16 %0 to i32 |
| 40 ret i32 %ret |
| 39 } | 41 } |
| 40 | 42 |
| 41 define <8 x i1> @__Sz_bitcast_i8_8xi1(i8 %a) { | 43 define <8 x i1> @__Sz_bitcast_i8_8xi1(i8 %a) { |
| 42 entry: | 44 entry: |
| 43 %0 = bitcast i8 %a to <8 x i1> | 45 %0 = bitcast i8 %a to <8 x i1> |
| 44 ret <8 x i1> %0 | 46 ret <8 x i1> %0 |
| 45 } | 47 } |
| 46 | 48 |
| 47 define <16 x i1> @__Sz_bitcast_i16_16xi1(i16 %a) { | 49 define <16 x i1> @__Sz_bitcast_i16_16xi1(i16 %a) { |
| 48 entry: | 50 entry: |
| 49 %0 = bitcast i16 %a to <16 x i1> | 51 %0 = bitcast i16 %a to <16 x i1> |
| 50 ret <16 x i1> %0 | 52 ret <16 x i1> %0 |
| 51 } | 53 } |
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