Add option to force filetype=asm for testing

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 28 matching lines @@
 declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
 declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
 declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32)
 declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32)
 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
 declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
 declare void @llvm.nacl.atomic.fence(i32)
 declare void @llvm.nacl.atomic.fence.all()
 declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
 
-@Global8 = internal global [1 x i8] zeroinitializer, align 1
-@Global16 = internal global [2 x i8] zeroinitializer, align 2
-@Global32 = internal global [4 x i8] zeroinitializer, align 4
-@Global64 = internal global [8 x i8] zeroinitializer, align 8
+@SzGlobal8 = internal global [1 x i8] zeroinitializer, align 1
+@SzGlobal16 = internal global [2 x i8] zeroinitializer, align 2
+@SzGlobal32 = internal global [4 x i8] zeroinitializer, align 4
+@SzGlobal64 = internal global [8 x i8] zeroinitializer, align 8
 
 ; NOTE: The LLC equivalent for 16-bit atomic operations are expanded
 ; as 32-bit operations. For Subzero, assume that real 16-bit operations
 ; will be usable (the validator will be fixed):
 ; https://code.google.com/p/nativeclient/issues/detail?id=2981
 
 ;;; Load
 
 ; x86 guarantees load/store to be atomic if naturally aligned.
 ; The PNaCl IR requires all atomic accesses to be naturally aligned.
@@ skipping 280 matching lines @@
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32-NEXT: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i64 @test_atomic_rmw_add_64_global(i64 %v) {
 entry:
-  %ptr = bitcast [8 x i8]* @Global64 to i64*
+  %ptr = bitcast [8 x i8]* @SzGlobal64 to i64*
   %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64_global
 ; ARM32-LABEL: test_atomic_rmw_add_64_global
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32-NEXT: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
@@ skipping 224 matching lines @@
 ; ARM32: ldrexb
 ; ARM32: orr
 ; ARM32: strexb
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i32 @test_atomic_rmw_or_8_global(i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
-  %ptr = bitcast [1 x i8]* @Global8 to i8*
+  %ptr = bitcast [1 x i8]* @SzGlobal8 to i8*
   %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
   %a_ext = zext i8 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_8_global
 ; ARM32-LABEL: test_atomic_rmw_or_8_global
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:Global8
-; ARM32: movt [[PTR]], #:upper16:Global8
+; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal8
+; ARM32: movt [[PTR]], #:upper16:SzGlobal8
 ; ARM32: dmb
 ; ARM32: ldrexb r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strexb
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
@@ skipping 12 matching lines @@
 ; ARM32: ldrexh
 ; ARM32: orr
 ; ARM32: strexh
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i32 @test_atomic_rmw_or_16_global(i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
-  %ptr = bitcast [2 x i8]* @Global16 to i16*
+  %ptr = bitcast [2 x i8]* @SzGlobal16 to i16*
   %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
   %a_ext = zext i16 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_16_global
 ; ARM32-LABEL: test_atomic_rmw_or_16_global
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:Global16
-; ARM32: movt [[PTR]], #:upper16:Global16
+; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal16
+; ARM32: movt [[PTR]], #:upper16:SzGlobal16
 ; ARM32: dmb
 ; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strexh
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32
 ; CHECK: mov eax,DWORD PTR
 ; CHECK: or [[REG:e[^a].]]
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
 ; CHECK: jne
 ; ARM32-LABEL: test_atomic_rmw_or_32
 ; ARM32: dmb
 ; ARM32: ldrex
 ; ARM32: orr
 ; ARM32: strex
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i32 @test_atomic_rmw_or_32_global(i32 %v) {
 entry:
-  %ptr = bitcast [4 x i8]* @Global32 to i32*
+  %ptr = bitcast [4 x i8]* @SzGlobal32 to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32_global
 ; ARM32-LABEL: test_atomic_rmw_or_32_global
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:Global32
-; ARM32: movt [[PTR]], #:upper16:Global32
+; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal32
+; ARM32: movt [[PTR]], #:upper16:SzGlobal32
 ; ARM32: dmb
 ; ARM32: ldrex r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strex
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
@@ skipping 691 matching lines @@
 
 ; Test the liveness / register allocation properties of the xadd instruction.
 ; Make sure we model that the Src register is modified and therefore it can't
 ; share a register with an overlapping live range, even if the result of the
 ; xadd instruction is unused.
 define internal void @test_xadd_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
-  %g = bitcast [4 x i8]* @Global32 to i32*
+  %g = bitcast [4 x i8]* @SzGlobal32 to i32*
   %unused = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %g, i32 %i, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_xadd_regalloc
 ;;; Some register will be used in the xadd instruction.
 ; O2: lock xadd DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure that register isn't used again, e.g. as the induction variable.
 ; O2-NOT: [[REG]]
 ; O2: ret
 
 ; Do the same test for the xchg instruction instead of xadd.
 define internal void @test_xchg_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
-  %g = bitcast [4 x i8]* @Global32 to i32*
+  %g = bitcast [4 x i8]* @SzGlobal32 to i32*
   %unused = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %g, i32 %i, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_xchg_regalloc
 ;;; Some register will be used in the xchg instruction.
 ; O2: xchg DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure that register isn't used again, e.g. as the induction variable.
 ; O2-NOT: [[REG]]
 ; O2: ret
 
 ; Same test for cmpxchg.
 define internal void @test_cmpxchg_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
-  %g = bitcast [4 x i8]* @Global32 to i32*
+  %g = bitcast [4 x i8]* @SzGlobal32 to i32*
   %unused = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %g, i32 %i, i32 %i, i32 6, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure eax isn't used again, e.g. as the induction variable.
 ; O2-NOT: eax
 ; O2: ret
 
 ; Same test for cmpxchg8b.
 define internal void @test_cmpxchg8b_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
-  %g = bitcast [8 x i8]* @Global64 to i64*
+  %g = bitcast [8 x i8]* @SzGlobal64 to i64*
   %i_64 = zext i32 %i to i64
   %unused = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %g, i64 %i_64, i64 %i_64, i32 6, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: {{eax|ecx|edx|ebx}}
 ; O2: pop ebx