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Issue 1531623007: Add option to force filetype=asm for testing (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Code review fixes. Tighter ABI checks. Created 4 years, 11 months ago
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« src/IceTargetLoweringX86BaseImpl.h ('K') | « tests_lit/llvm2ice_tests/contract.ll ('k') | tests_lit/llvm2ice_tests/elf_container.ll » ('j') | tests_lit/llvm2ice_tests/loop-nest-depth.ll » ('J')
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1 ; Simple test of signed and unsigned integer conversions. 1 ; Simple test of signed and unsigned integer conversions.
2 2
3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
4 ; RUN: --target x8632 -i %s --args -O2 \ 4 ; RUN: --target x8632 -i %s --args -O2 \
5 ; RUN: | %if --need=target_X8632 --command FileCheck %s 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s
6 6
7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
8 ; RUN: --target x8632 -i %s --args -Om1 \ 8 ; RUN: --target x8632 -i %s --args -Om1 \
9 ; RUN: | %if --need=target_X8632 --command FileCheck %s 9 ; RUN: | %if --need=target_X8632 --command FileCheck %s
10 10
(...skipping 30 matching lines...) Expand all
41 store i16 %v1, i16* %__3, align 1 41 store i16 %v1, i16* %__3, align 1
42 %v2 = sext i8 %v0 to i32 42 %v2 = sext i8 %v0 to i32
43 %__5 = bitcast [4 x i8]* @i32v to i32* 43 %__5 = bitcast [4 x i8]* @i32v to i32*
44 store i32 %v2, i32* %__5, align 1 44 store i32 %v2, i32* %__5, align 1
45 %v3 = sext i8 %v0 to i64 45 %v3 = sext i8 %v0 to i64
46 %__7 = bitcast [8 x i8]* @i64v to i64* 46 %__7 = bitcast [8 x i8]* @i64v to i64*
47 store i64 %v3, i64* %__7, align 1 47 store i64 %v3, i64* %__7, align 1
48 ret void 48 ret void
49 } 49 }
50 ; CHECK-LABEL: from_int8 50 ; CHECK-LABEL: from_int8
51 ; CHECK: mov {{.*}},BYTE PTR 51 ; CHECK: mov {{.*}},{{(BYTE PTR)?}}
52 ; CHECK: movsx e{{.*}},{{[a-d]l|BYTE PTR}} 52 ; CHECK: movsx {{.*}},{{[a-d]l|BYTE PTR}}
53 ; CHECK: mov WORD PTR 53 ; CHECK: mov {{(WORD PTR)?}}
54 ; CHECK: movsx 54 ; CHECK: movsx
55 ; CHECK: mov DWORD PTR 55 ; CHECK: mov {{(DWORD PTR)?}}
56 ; CHECK: movsx 56 ; CHECK: movsx
57 ; CHECK: sar {{.*}},0x1f 57 ; CHECK: sar {{.*}},0x1f
58 ; CHECK-DAG: ds:0x0,{{.*}}i64v 58 ; CHECK-DAG: ds:0x{{.}},{{.*}}{{(i64v)|(.bss)}}
59 ; CHECK-DAG: ds:0x4,{{.*}}i64v 59 ; CHECK-DAG: ds:0x{{.}},{{.*}}{{(i64v)|(.bss)}}
60 60
61 ; ARM32-LABEL: from_int8 61 ; ARM32-LABEL: from_int8
62 ; ARM32: movw {{.*}}i8v 62 ; ARM32: movw {{.*}}i8v
63 ; ARM32: ldrb 63 ; ARM32: ldrb
64 ; ARM32: sxtb 64 ; ARM32: sxtb
65 ; ARM32: movw {{.*}}i16v 65 ; ARM32: movw {{.*}}i16v
66 ; ARM32: strh 66 ; ARM32: strh
67 ; ARM32: sxtb 67 ; ARM32: sxtb
68 ; ARM32: movw {{.*}}i32v 68 ; ARM32: movw {{.*}}i32v
69 ; ARM32: str r 69 ; ARM32: str r
(...skipping 12 matching lines...) Expand all
82 store i8 %v1, i8* %__3, align 1 82 store i8 %v1, i8* %__3, align 1
83 %v2 = sext i16 %v0 to i32 83 %v2 = sext i16 %v0 to i32
84 %__5 = bitcast [4 x i8]* @i32v to i32* 84 %__5 = bitcast [4 x i8]* @i32v to i32*
85 store i32 %v2, i32* %__5, align 1 85 store i32 %v2, i32* %__5, align 1
86 %v3 = sext i16 %v0 to i64 86 %v3 = sext i16 %v0 to i64
87 %__7 = bitcast [8 x i8]* @i64v to i64* 87 %__7 = bitcast [8 x i8]* @i64v to i64*
88 store i64 %v3, i64* %__7, align 1 88 store i64 %v3, i64* %__7, align 1
89 ret void 89 ret void
90 } 90 }
91 ; CHECK-LABEL: from_int16 91 ; CHECK-LABEL: from_int16
92 ; CHECK: mov {{.*}},WORD PTR 92 ; CHECK: mov {{.*}},{{(WORD PTR)?}}
93 ; CHECK: 0x0 {{.*}}i16v 93 ; CHECK: 0x{{.}} {{.*}}{{(i16v)|(.bss)}}
94 ; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}} 94 ; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
95 ; CHECK: 0x0,{{.*}}i32v 95 ; CHECK: 0x{{.}},{{.*}}{{(i32v)|(.bss)}}
96 ; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}} 96 ; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
97 ; CHECK: sar {{.*}},0x1f 97 ; CHECK: sar {{.*}},0x1f
98 ; CHECK: 0x0,{{.*}}i64v 98 ; CHECK: 0x{{.}},{{.*}}{{(i64v)|(.bss)}}
99 99
100 ; ARM32-LABEL: from_int16 100 ; ARM32-LABEL: from_int16
101 ; ARM32: movw {{.*}}i16v 101 ; ARM32: movw {{.*}}i16v
102 ; ARM32: ldrh 102 ; ARM32: ldrh
103 ; ARM32: movw {{.*}}i8v 103 ; ARM32: movw {{.*}}i8v
104 ; ARM32: strb 104 ; ARM32: strb
105 ; ARM32: sxth 105 ; ARM32: sxth
106 ; ARM32: movw {{.*}}i32v 106 ; ARM32: movw {{.*}}i32v
107 ; ARM32: str r 107 ; ARM32: str r
108 ; ARM32: sxth 108 ; ARM32: sxth
(...skipping 10 matching lines...) Expand all
119 store i8 %v1, i8* %__3, align 1 119 store i8 %v1, i8* %__3, align 1
120 %v2 = trunc i32 %v0 to i16 120 %v2 = trunc i32 %v0 to i16
121 %__5 = bitcast [2 x i8]* @i16v to i16* 121 %__5 = bitcast [2 x i8]* @i16v to i16*
122 store i16 %v2, i16* %__5, align 1 122 store i16 %v2, i16* %__5, align 1
123 %v3 = sext i32 %v0 to i64 123 %v3 = sext i32 %v0 to i64
124 %__7 = bitcast [8 x i8]* @i64v to i64* 124 %__7 = bitcast [8 x i8]* @i64v to i64*
125 store i64 %v3, i64* %__7, align 1 125 store i64 %v3, i64* %__7, align 1
126 ret void 126 ret void
127 } 127 }
128 ; CHECK-LABEL: from_int32 128 ; CHECK-LABEL: from_int32
129 ; CHECK: 0x0 {{.*}} i32v 129 ; CHECK: 0x{{.}} {{.*}} {{(i32v)|(.bss)}}
130 ; CHECK: 0x0,{{.*}} i8v 130 ; CHECK: 0x{{.}},{{.*}} {{(i8v)|(.bss)}}
131 ; CHECK: 0x0,{{.*}} i16v 131 ; CHECK: 0x{{.}},{{.*}} {{(i16v)|(.bss)}}
132 ; CHECK: sar {{.*}},0x1f 132 ; CHECK: sar {{.*}},0x1f
133 ; CHECK: 0x0,{{.*}} i64v 133 ; CHECK: 0x{{.}},{{.*}} {{(i64v)|(.bss)}}
134 134
135 ; ARM32-LABEL: from_int32 135 ; ARM32-LABEL: from_int32
136 ; ARM32: movw {{.*}}i32v 136 ; ARM32: movw {{.*}}i32v
137 ; ARM32: ldr r 137 ; ARM32: ldr r
138 ; ARM32: movw {{.*}}i8v 138 ; ARM32: movw {{.*}}i8v
139 ; ARM32: strb 139 ; ARM32: strb
140 ; ARM32: movw {{.*}}i16v 140 ; ARM32: movw {{.*}}i16v
141 ; ARM32: strh 141 ; ARM32: strh
142 ; ARM32: asr 142 ; ARM32: asr
143 ; ARM32: movw {{.*}}i64v 143 ; ARM32: movw {{.*}}i64v
144 ; ARM32: str r 144 ; ARM32: str r
145 145
146 define internal void @from_int64() { 146 define internal void @from_int64() {
147 entry: 147 entry:
148 %__0 = bitcast [8 x i8]* @i64v to i64* 148 %__0 = bitcast [8 x i8]* @i64v to i64*
149 %v0 = load i64, i64* %__0, align 1 149 %v0 = load i64, i64* %__0, align 1
150 %v1 = trunc i64 %v0 to i8 150 %v1 = trunc i64 %v0 to i8
151 %__3 = bitcast [1 x i8]* @i8v to i8* 151 %__3 = bitcast [1 x i8]* @i8v to i8*
152 store i8 %v1, i8* %__3, align 1 152 store i8 %v1, i8* %__3, align 1
153 %v2 = trunc i64 %v0 to i16 153 %v2 = trunc i64 %v0 to i16
154 %__5 = bitcast [2 x i8]* @i16v to i16* 154 %__5 = bitcast [2 x i8]* @i16v to i16*
155 store i16 %v2, i16* %__5, align 1 155 store i16 %v2, i16* %__5, align 1
156 %v3 = trunc i64 %v0 to i32 156 %v3 = trunc i64 %v0 to i32
157 %__7 = bitcast [4 x i8]* @i32v to i32* 157 %__7 = bitcast [4 x i8]* @i32v to i32*
158 store i32 %v3, i32* %__7, align 1 158 store i32 %v3, i32* %__7, align 1
159 ret void 159 ret void
160 } 160 }
161 ; CHECK-LABEL: from_int64 161 ; CHECK-LABEL: from_int64
162 ; CHECK: 0x0 {{.*}} i64v 162 ; CHECK: 0x{{.}} {{.*}} {{(i64v)|(.bss)}}
163 ; CHECK: 0x0,{{.*}} i8v 163 ; CHECK: 0x{{.}},{{.*}} {{(i8v)|(.bss)}}
164 ; CHECK: 0x0,{{.*}} i16v 164 ; CHECK: 0x{{.}},{{.*}} {{(i16v)|(.bss)}}
165 ; CHECK: 0x0,{{.*}} i32v 165 ; CHECK: 0x{{.}},{{.*}} {{(i32v)|(.bss)}}
166 166
167 ; ARM32-LABEL: from_int64 167 ; ARM32-LABEL: from_int64
168 ; ARM32: movw {{.*}}i64v 168 ; ARM32: movw {{.*}}i64v
169 ; ARM32: ldr r 169 ; ARM32: ldr r
170 ; ARM32: movw {{.*}}i8v 170 ; ARM32: movw {{.*}}i8v
171 ; ARM32: strb 171 ; ARM32: strb
172 ; ARM32: movw {{.*}}i16v 172 ; ARM32: movw {{.*}}i16v
173 ; ARM32: strh 173 ; ARM32: strh
174 ; ARM32: movw {{.*}}i32v 174 ; ARM32: movw {{.*}}i32v
175 ; ARM32: str r 175 ; ARM32: str r
176 176
177 define internal void @from_uint8() { 177 define internal void @from_uint8() {
178 entry: 178 entry:
179 %__0 = bitcast [1 x i8]* @u8v to i8* 179 %__0 = bitcast [1 x i8]* @u8v to i8*
180 %v0 = load i8, i8* %__0, align 1 180 %v0 = load i8, i8* %__0, align 1
181 %v1 = zext i8 %v0 to i16 181 %v1 = zext i8 %v0 to i16
182 %__3 = bitcast [2 x i8]* @i16v to i16* 182 %__3 = bitcast [2 x i8]* @i16v to i16*
183 store i16 %v1, i16* %__3, align 1 183 store i16 %v1, i16* %__3, align 1
184 %v2 = zext i8 %v0 to i32 184 %v2 = zext i8 %v0 to i32
185 %__5 = bitcast [4 x i8]* @i32v to i32* 185 %__5 = bitcast [4 x i8]* @i32v to i32*
186 store i32 %v2, i32* %__5, align 1 186 store i32 %v2, i32* %__5, align 1
187 %v3 = zext i8 %v0 to i64 187 %v3 = zext i8 %v0 to i64
188 %__7 = bitcast [8 x i8]* @i64v to i64* 188 %__7 = bitcast [8 x i8]* @i64v to i64*
189 store i64 %v3, i64* %__7, align 1 189 store i64 %v3, i64* %__7, align 1
190 ret void 190 ret void
191 } 191 }
192 ; CHECK-LABEL: from_uint8 192 ; CHECK-LABEL: from_uint8
193 ; CHECK: 0x0 {{.*}} u8v 193 ; CHECK: 0x{{.*}} {{.*}} {{(u8v)|(.bss)}}
194 ; CHECK: movzx e{{.*}},{{[a-d]l|BYTE PTR}} 194 ; CHECK: movzx {{.*}},{{[a-d]l|BYTE PTR}}
195 ; CHECK: 0x0,{{.*}} i16v 195 ; CHECK: 0x{{.}},{{.*}} {{(i16v)|(.bss)}}
196 ; CHECK: movzx 196 ; CHECK: movzx
197 ; CHECK: 0x0,{{.*}} i32v 197 ; CHECK: 0x{{.}},{{.*}} {{(i32v)|(.bss)}}
198 ; CHECK: movzx 198 ; CHECK: movzx
199 ; CHECK: mov {{.*}},0x0 199 ; CHECK: mov {{.*}},0x0
200 ; CHECK: 0x0,{{.*}} i64v 200 ; CHECK: 0x{{.}},{{.*}} {{(i64v)|(.bss)}}
201 201
202 ; ARM32-LABEL: from_uint8 202 ; ARM32-LABEL: from_uint8
203 ; ARM32: movw {{.*}}u8v 203 ; ARM32: movw {{.*}}u8v
204 ; ARM32: ldrb 204 ; ARM32: ldrb
205 ; ARM32: uxtb 205 ; ARM32: uxtb
206 ; ARM32: movw {{.*}}i16v 206 ; ARM32: movw {{.*}}i16v
207 ; ARM32: strh 207 ; ARM32: strh
208 ; ARM32: uxtb 208 ; ARM32: uxtb
209 ; ARM32: movw {{.*}}i32v 209 ; ARM32: movw {{.*}}i32v
210 ; ARM32: str r 210 ; ARM32: str r
(...skipping 11 matching lines...) Expand all
222 store i8 %v1, i8* %__3, align 1 222 store i8 %v1, i8* %__3, align 1
223 %v2 = zext i16 %v0 to i32 223 %v2 = zext i16 %v0 to i32
224 %__5 = bitcast [4 x i8]* @i32v to i32* 224 %__5 = bitcast [4 x i8]* @i32v to i32*
225 store i32 %v2, i32* %__5, align 1 225 store i32 %v2, i32* %__5, align 1
226 %v3 = zext i16 %v0 to i64 226 %v3 = zext i16 %v0 to i64
227 %__7 = bitcast [8 x i8]* @i64v to i64* 227 %__7 = bitcast [8 x i8]* @i64v to i64*
228 store i64 %v3, i64* %__7, align 1 228 store i64 %v3, i64* %__7, align 1
229 ret void 229 ret void
230 } 230 }
231 ; CHECK-LABEL: from_uint16 231 ; CHECK-LABEL: from_uint16
232 ; CHECK: 0x0 {{.*}} u16v 232 ; CHECK: 0x{{.*}} {{.*}} {{(u16v)|(.bss)}}
233 ; CHECK: 0x0,{{.*}} i8v 233 ; CHECK: 0x{{.}},{{.*}} {{(i8v)|(.bss)}}
234 ; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}} 234 ; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
235 ; CHECK: 0x0,{{.*}} i32v 235 ; CHECK: 0x{{.}},{{.*}} {{(i32v)|(.bss)}}
236 ; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}} 236 ; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
237 ; CHECK: mov {{.*}},0x0 237 ; CHECK: mov {{.*}},0x0
238 ; CHECK: 0x0,{{.*}} i64v 238 ; CHECK: 0x{{.}},{{.*}} {{(i64v)|(.bss)}}
239 239
240 ; ARM32-LABEL: from_uint16 240 ; ARM32-LABEL: from_uint16
241 ; ARM32: movw {{.*}}u16v 241 ; ARM32: movw {{.*}}u16v
242 ; ARM32: ldrh 242 ; ARM32: ldrh
243 ; ARM32: movw {{.*}}i8v 243 ; ARM32: movw {{.*}}i8v
244 ; ARM32: strb 244 ; ARM32: strb
245 ; ARM32: uxth 245 ; ARM32: uxth
246 ; ARM32: movw {{.*}}i32v 246 ; ARM32: movw {{.*}}i32v
247 ; ARM32: str r 247 ; ARM32: str r
248 ; ARM32: uxth 248 ; ARM32: uxth
(...skipping 10 matching lines...) Expand all
259 store i8 %v1, i8* %__3, align 1 259 store i8 %v1, i8* %__3, align 1
260 %v2 = trunc i32 %v0 to i16 260 %v2 = trunc i32 %v0 to i16
261 %__5 = bitcast [2 x i8]* @i16v to i16* 261 %__5 = bitcast [2 x i8]* @i16v to i16*
262 store i16 %v2, i16* %__5, align 1 262 store i16 %v2, i16* %__5, align 1
263 %v3 = zext i32 %v0 to i64 263 %v3 = zext i32 %v0 to i64
264 %__7 = bitcast [8 x i8]* @i64v to i64* 264 %__7 = bitcast [8 x i8]* @i64v to i64*
265 store i64 %v3, i64* %__7, align 1 265 store i64 %v3, i64* %__7, align 1
266 ret void 266 ret void
267 } 267 }
268 ; CHECK-LABEL: from_uint32 268 ; CHECK-LABEL: from_uint32
269 ; CHECK: 0x0 {{.*}} u32v 269 ; CHECK: 0x{{.*}} {{.*}} {{(u32v)|(.bss)}}
270 ; CHECK: 0x0,{{.*}} i8v 270 ; CHECK: 0x{{.}},{{.*}} {{(i8v)|(.bss)}}
271 ; CHECK: 0x0,{{.*}} i16v 271 ; CHECK: 0x{{.}},{{.*}} {{(i16v)|(.bss)}}
272 ; CHECK: mov {{.*}},0x0 272 ; CHECK: mov {{.*}},0x0
273 ; CHECK: 0x0,{{.*}} i64v 273 ; CHECK: 0x{{.}},{{.*}} {{(i64v)|(.bss)}}
274 274
275 ; ARM32-LABEL: from_uint32 275 ; ARM32-LABEL: from_uint32
276 ; ARM32: movw {{.*}}u32v 276 ; ARM32: movw {{.*}}u32v
277 ; ARM32: ldr r 277 ; ARM32: ldr r
278 ; ARM32: movw {{.*}}i8v 278 ; ARM32: movw {{.*}}i8v
279 ; ARM32: strb 279 ; ARM32: strb
280 ; ARM32: movw {{.*}}i16v 280 ; ARM32: movw {{.*}}i16v
281 ; ARM32: strh 281 ; ARM32: strh
282 ; ARM32: mov {{.*}}, #0 282 ; ARM32: mov {{.*}}, #0
283 ; ARM32: movw {{.*}}i64v 283 ; ARM32: movw {{.*}}i64v
284 ; ARM32: str r 284 ; ARM32: str r
285 285
286 define internal void @from_uint64() { 286 define internal void @from_uint64() {
287 entry: 287 entry:
288 %__0 = bitcast [8 x i8]* @u64v to i64* 288 %__0 = bitcast [8 x i8]* @u64v to i64*
289 %v0 = load i64, i64* %__0, align 1 289 %v0 = load i64, i64* %__0, align 1
290 %v1 = trunc i64 %v0 to i8 290 %v1 = trunc i64 %v0 to i8
291 %__3 = bitcast [1 x i8]* @i8v to i8* 291 %__3 = bitcast [1 x i8]* @i8v to i8*
292 store i8 %v1, i8* %__3, align 1 292 store i8 %v1, i8* %__3, align 1
293 %v2 = trunc i64 %v0 to i16 293 %v2 = trunc i64 %v0 to i16
294 %__5 = bitcast [2 x i8]* @i16v to i16* 294 %__5 = bitcast [2 x i8]* @i16v to i16*
295 store i16 %v2, i16* %__5, align 1 295 store i16 %v2, i16* %__5, align 1
296 %v3 = trunc i64 %v0 to i32 296 %v3 = trunc i64 %v0 to i32
297 %__7 = bitcast [4 x i8]* @i32v to i32* 297 %__7 = bitcast [4 x i8]* @i32v to i32*
298 store i32 %v3, i32* %__7, align 1 298 store i32 %v3, i32* %__7, align 1
299 ret void 299 ret void
300 } 300 }
301 ; CHECK-LABEL: from_uint64 301 ; CHECK-LABEL: from_uint64
302 ; CHECK: 0x0 {{.*}} u64v 302 ; CHECK: 0x{{.*}} {{.*}} {{(u64v)|(.bss)}}
303 ; CHECK: 0x0,{{.*}} i8v 303 ; CHECK: 0x{{.}},{{.*}} {{(i8v)|(.bss)}}
304 ; CHECK: 0x0,{{.*}} i16v 304 ; CHECK: 0x{{.}},{{.*}} {{(i16v)|(.bss)}}
305 ; CHECK: 0x0,{{.*}} i32v 305 ; CHECK: 0x{{.}},{{.*}} {{(i32v)|(.bss)}}
306 306
307 ; ARM32-LABEL: from_uint64 307 ; ARM32-LABEL: from_uint64
308 ; ARM32: movw {{.*}}u64v 308 ; ARM32: movw {{.*}}u64v
309 ; ARM32: ldr r 309 ; ARM32: ldr r
310 ; ARM32: movw {{.*}}i8v 310 ; ARM32: movw {{.*}}i8v
311 ; ARM32: strb 311 ; ARM32: strb
312 ; ARM32: movw {{.*}}i16v 312 ; ARM32: movw {{.*}}i16v
313 ; ARM32: strh 313 ; ARM32: strh
314 ; ARM32: movw {{.*}}i32v 314 ; ARM32: movw {{.*}}i32v
315 ; ARM32: str r 315 ; ARM32: str r
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« src/IceTargetLoweringX86BaseImpl.h ('K') | « tests_lit/llvm2ice_tests/contract.ll ('k') | tests_lit/llvm2ice_tests/elf_container.ll » ('j') | tests_lit/llvm2ice_tests/loop-nest-depth.ll » ('J')

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