add RBIT instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 6a31ef215bc11388a61e42be8324c612fb2d9a02..bd22b1418733dc14e53560df06e696fbc21a22e1 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -1797,21 +1797,39 @@ void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
             MulName);
 }
 
-void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpSrc,
+void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode,
+                              const Operand *OpRd, const Operand *OpRm,
+                              const char *InstName) {
+  IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
+  IValueT Rm = encodeRegister(OpRm, "Rm", InstName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding =
+      (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm,
+                          CondARM32::Cond Cond) {
+  // RBIT - ARM section A8.8.144, encoding A1:
+  //   rbit<c> <Rd>, <Rm>
+  //
+  // cccc011011111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
+  constexpr const char *RbitName = "rev";
+  constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 |
+                                 B17 | B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RbitOpcode, OpRd, OpRm, RbitName);
+}
+
+void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpRm,
                          CondARM32::Cond Cond) {
   // REV - ARM section A8.8.145, encoding A1:
-  //   rev <Rd>, <Rm>
+  //   rev<c> <Rd>, <Rm>
   //
   // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
   constexpr const char *RevName = "rev";
-  IValueT Rd = encodeRegister(OpRd, "Rd", RevName);
-  IValueT Rm = encodeRegister(OpSrc, "Rm", RevName);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  constexpr IValueT Opcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
-                             B16 | B11 | B10 | B9 | B8 | B5 | B4;
-  IValueT Encoding =
-      (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
-  emitInst(Encoding);
+  constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
+                                B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RevOpcode, OpRd, OpRm, RevName);
 }
 
 void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,