add RBIT instruction to the ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 247 matching lines @@
   void pop(const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void popList(const IValueT Registers, CondARM32::Cond Cond);
 
   void push(const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void pushList(const IValueT Registers, CondARM32::Cond Cond);
 
-  void rev(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+  void rbit(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
+
+  void rev(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
 
   void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
@@ skipping 98 matching lines @@
                   const char *InstName);
 
   // Emit ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond,
   // ooo=InstType, l=isLoad, b=isByte, and
   // aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that Address is assumed to be
   // defined by decodeAddress() in IceAssemblerARM32.cpp.
   void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
                  bool IsByte, IValueT Rt, IValueT Address,
                  const char *InstName);
 
+  // Emit ccccxxxxxxxxxxxxddddxxxxxxxxmmmm where cccc=Cond,
+  // xxxxxxxxxxxx0000xxxxxxxx0000=Opcode, dddd=Rd, and mmmm=Rm.
+  void emitRdRm(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRd,
+                const Operand *OpRm, const char *InstName);
+
   // Emit ldr/ldrb/str/strb instruction with given address.
   void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
                  const Operand *OpAddress, const TargetInfo &TInfo,
                  const char *InstName);
 
   // Emit ldrh/ldrd/strh/strd instruction with given address using encoding 3.
   void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt,
                      const Operand *OpAddress, const TargetInfo &TInfo,
                      const char *InstName);
 
@@ skipping 52 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H