add RBIT instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1761 matching lines @@
   IValueT Rm = encodeRegister(OpSrc1, "Rm", MulName);
   verifyRegNotPc(Rd, "Rd", MulName);
   verifyRegNotPc(Rn, "Rn", MulName);
   verifyRegNotPc(Rm, "Rm", MulName);
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT MulOpcode = 0;
   emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags,
             MulName);
 }
 
-void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpSrc,
-                         CondARM32::Cond Cond) {
-  // REV - ARM section A8.8.145, encoding A1:
-  //   rev <Rd>, <Rm>
-  //
-  // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
-  constexpr const char *RevName = "rev";
-  IValueT Rd = encodeRegister(OpRd, "Rd", RevName);
-  IValueT Rm = encodeRegister(OpSrc, "Rm", RevName);
+void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode,
+                              const Operand *OpRd, const Operand *OpRm,
+                              const char *InstName) {
+  IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
+  IValueT Rm = encodeRegister(OpRm, "Rm", InstName);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  constexpr IValueT Opcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
-                             B16 | B11 | B10 | B9 | B8 | B5 | B4;
   IValueT Encoding =
       (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm,
+                          CondARM32::Cond Cond) {
+  // RBIT - ARM section A8.8.144, encoding A1:
+  //   rbit<c> <Rd>, <Rm>
+  //
+  // cccc011011111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
+  constexpr const char *RbitName = "rev";
+  constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 |
+                                 B17 | B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RbitOpcode, OpRd, OpRm, RbitName);
+}
+
+void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpRm,
+                         CondARM32::Cond Cond) {
+  // REV - ARM section A8.8.145, encoding A1:
+  //   rev<c> <Rd>, <Rm>
+  //
+  // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
+  constexpr const char *RevName = "rev";
+  constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
+                                B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RevOpcode, OpRd, OpRm, RevName);
+}
+
 void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // RSB (immediate) - ARM section A8.8.152, encoding A1.
   //   rsb{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010011snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=setFlags and iiiiiiiiiiii defines the RotatedImm8 value.
   //
   // RSB (register) - ARM section A8.8.163, encoding A1.
@@ skipping 147 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice