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Side by Side Diff: src/compiler/register-allocator.cc

Issue 1528983005: [turbofan] Print APIs for live ranges. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/linkage.h" 6 #include "src/compiler/linkage.h"
7 #include "src/compiler/register-allocator.h" 7 #include "src/compiler/register-allocator.h"
8 #include "src/string-stream.h" 8 #include "src/string-stream.h"
9 9
10 namespace v8 { 10 namespace v8 {
(...skipping 212 matching lines...) Expand 10 before | Expand all | Expand 10 after
223 UseInterval* UseInterval::SplitAt(LifetimePosition pos, Zone* zone) { 223 UseInterval* UseInterval::SplitAt(LifetimePosition pos, Zone* zone) {
224 DCHECK(Contains(pos) && pos != start()); 224 DCHECK(Contains(pos) && pos != start());
225 auto after = new (zone) UseInterval(pos, end_); 225 auto after = new (zone) UseInterval(pos, end_);
226 after->next_ = next_; 226 after->next_ = next_;
227 next_ = nullptr; 227 next_ = nullptr;
228 end_ = pos; 228 end_ = pos;
229 return after; 229 return after;
230 } 230 }
231 231
232 232
233 void LifetimePosition::Print() const {
234 OFStream os(stdout);
235 os << *this << std::endl;
236 }
237
238
233 std::ostream& operator<<(std::ostream& os, const LifetimePosition pos) { 239 std::ostream& operator<<(std::ostream& os, const LifetimePosition pos) {
234 os << '@' << pos.ToInstructionIndex(); 240 os << '@' << pos.ToInstructionIndex();
235 if (pos.IsGapPosition()) { 241 if (pos.IsGapPosition()) {
236 os << 'g'; 242 os << 'g';
237 } else { 243 } else {
238 os << 'i'; 244 os << 'i';
239 } 245 }
240 if (pos.IsStart()) { 246 if (pos.IsStart()) {
241 os << 's'; 247 os << 's';
242 } else { 248 } else {
(...skipping 414 matching lines...) Expand 10 before | Expand all | Expand 10 after
657 for (auto interval = first_interval(); interval != nullptr; 663 for (auto interval = first_interval(); interval != nullptr;
658 interval = interval->next()) { 664 interval = interval->next()) {
659 size_ += (interval->end().value() - interval->start().value()); 665 size_ += (interval->end().value() - interval->start().value());
660 } 666 }
661 } 667 }
662 668
663 return static_cast<unsigned>(size_); 669 return static_cast<unsigned>(size_);
664 } 670 }
665 671
666 672
673 void LiveRange::Print(const RegisterConfiguration* config,
674 bool with_children) const {
675 OFStream os(stdout);
676 PrintableLiveRange wrapper;
677 wrapper.register_configuration_ = config;
678 for (const LiveRange* i = this; i != nullptr; i = i->next()) {
679 wrapper.range_ = i;
680 os << wrapper << std::endl;
681 if (!with_children) break;
682 }
683 }
684
685
686 void LiveRange::Print(bool with_children) const {
687 const RegisterConfiguration* config =
688 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
689 Print(config, with_children);
690 }
691
692
667 struct TopLevelLiveRange::SpillMoveInsertionList : ZoneObject { 693 struct TopLevelLiveRange::SpillMoveInsertionList : ZoneObject {
668 SpillMoveInsertionList(int gap_index, InstructionOperand* operand, 694 SpillMoveInsertionList(int gap_index, InstructionOperand* operand,
669 SpillMoveInsertionList* next) 695 SpillMoveInsertionList* next)
670 : gap_index(gap_index), operand(operand), next(next) {} 696 : gap_index(gap_index), operand(operand), next(next) {}
671 const int gap_index; 697 const int gap_index;
672 InstructionOperand* const operand; 698 InstructionOperand* const operand;
673 SpillMoveInsertionList* const next; 699 SpillMoveInsertionList* const next;
674 }; 700 };
675 701
676 702
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1173 } else { 1199 } else {
1174 tail->set_next(current); 1200 tail->set_next(current);
1175 } 1201 }
1176 tail = current; 1202 tail = current;
1177 current = current->next(); 1203 current = current->next();
1178 } 1204 }
1179 // Other list is empty => we are done 1205 // Other list is empty => we are done
1180 } 1206 }
1181 1207
1182 1208
1209 void SpillRange::Print() const {
1210 OFStream os(stdout);
1211 os << "{" << std::endl;
1212 for (TopLevelLiveRange* range : live_ranges()) {
1213 os << range->vreg() << " ";
1214 }
1215 os << std::endl;
1216
1217 for (UseInterval* i = interval(); i != nullptr; i = i->next()) {
1218 os << '[' << i->start() << ", " << i->end() << ')' << std::endl;
1219 }
1220 os << "}" << std::endl;
1221 }
1222
1223
1183 RegisterAllocationData::PhiMapValue::PhiMapValue(PhiInstruction* phi, 1224 RegisterAllocationData::PhiMapValue::PhiMapValue(PhiInstruction* phi,
1184 const InstructionBlock* block, 1225 const InstructionBlock* block,
1185 Zone* zone) 1226 Zone* zone)
1186 : phi_(phi), 1227 : phi_(phi),
1187 block_(block), 1228 block_(block),
1188 incoming_operands_(zone), 1229 incoming_operands_(zone),
1189 assigned_register_(kUnassignedRegister) { 1230 assigned_register_(kUnassignedRegister) {
1190 incoming_operands_.reserve(phi->operands().size()); 1231 incoming_operands_.reserve(phi->operands().size());
1191 } 1232 }
1192 1233
(...skipping 222 matching lines...) Expand 10 before | Expand all | Expand 10 after
1415 } 1456 }
1416 1457
1417 1458
1418 bool RegisterAllocationData::IsBlockBoundary(LifetimePosition pos) const { 1459 bool RegisterAllocationData::IsBlockBoundary(LifetimePosition pos) const {
1419 return pos.IsFullStart() && 1460 return pos.IsFullStart() &&
1420 code()->GetInstructionBlock(pos.ToInstructionIndex())->code_start() == 1461 code()->GetInstructionBlock(pos.ToInstructionIndex())->code_start() ==
1421 pos.ToInstructionIndex(); 1462 pos.ToInstructionIndex();
1422 } 1463 }
1423 1464
1424 1465
1425 void RegisterAllocationData::Print(
1426 const InstructionSequence* instructionSequence) {
1427 OFStream os(stdout);
1428 PrintableInstructionSequence wrapper;
1429 wrapper.register_configuration_ = config();
1430 wrapper.sequence_ = instructionSequence;
1431 os << wrapper << std::endl;
1432 }
1433
1434
1435 void RegisterAllocationData::Print(const Instruction* instruction) {
1436 OFStream os(stdout);
1437 PrintableInstruction wrapper;
1438 wrapper.instr_ = instruction;
1439 wrapper.register_configuration_ = config();
1440 os << wrapper << std::endl;
1441 }
1442
1443
1444 void RegisterAllocationData::Print(const LiveRange* range, bool with_children) {
1445 OFStream os(stdout);
1446 PrintableLiveRange wrapper;
1447 wrapper.register_configuration_ = config();
1448 for (const LiveRange* i = range; i != nullptr; i = i->next()) {
1449 wrapper.range_ = i;
1450 os << wrapper << std::endl;
1451 if (!with_children) break;
1452 }
1453 }
1454
1455
1456 void RegisterAllocationData::Print(const InstructionOperand& op) {
1457 OFStream os(stdout);
1458 PrintableInstructionOperand wrapper;
1459 wrapper.register_configuration_ = config();
1460 wrapper.op_ = op;
1461 os << wrapper << std::endl;
1462 }
1463
1464
1465 void RegisterAllocationData::Print(const MoveOperands* move) {
1466 OFStream os(stdout);
1467 PrintableInstructionOperand wrapper;
1468 wrapper.register_configuration_ = config();
1469 wrapper.op_ = move->destination();
1470 os << wrapper << " = ";
1471 wrapper.op_ = move->source();
1472 os << wrapper << std::endl;
1473 }
1474
1475
1476 void RegisterAllocationData::Print(const SpillRange* spill_range) {
1477 OFStream os(stdout);
1478 os << "{" << std::endl;
1479 for (TopLevelLiveRange* range : spill_range->live_ranges()) {
1480 os << range->vreg() << " ";
1481 }
1482 os << std::endl;
1483
1484 for (UseInterval* interval = spill_range->interval(); interval != nullptr;
1485 interval = interval->next()) {
1486 os << '[' << interval->start() << ", " << interval->end() << ')'
1487 << std::endl;
1488 }
1489 os << "}" << std::endl;
1490 }
1491
1492
1493 ConstraintBuilder::ConstraintBuilder(RegisterAllocationData* data) 1466 ConstraintBuilder::ConstraintBuilder(RegisterAllocationData* data)
1494 : data_(data) {} 1467 : data_(data) {}
1495 1468
1496 1469
1497 InstructionOperand* ConstraintBuilder::AllocateFixed( 1470 InstructionOperand* ConstraintBuilder::AllocateFixed(
1498 UnallocatedOperand* operand, int pos, bool is_tagged) { 1471 UnallocatedOperand* operand, int pos, bool is_tagged) {
1499 TRACE("Allocating fixed reg for op %d\n", operand->virtual_register()); 1472 TRACE("Allocating fixed reg for op %d\n", operand->virtual_register());
1500 DCHECK(operand->HasFixedPolicy()); 1473 DCHECK(operand->HasFixedPolicy());
1501 InstructionOperand allocated; 1474 InstructionOperand allocated;
1502 MachineRepresentation rep = InstructionSequence::DefaultRepresentation(); 1475 MachineRepresentation rep = InstructionSequence::DefaultRepresentation();
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3449 auto eliminate = moves->PrepareInsertAfter(move); 3422 auto eliminate = moves->PrepareInsertAfter(move);
3450 to_insert.push_back(move); 3423 to_insert.push_back(move);
3451 if (eliminate != nullptr) to_eliminate.push_back(eliminate); 3424 if (eliminate != nullptr) to_eliminate.push_back(eliminate);
3452 } 3425 }
3453 } 3426 }
3454 3427
3455 3428
3456 } // namespace compiler 3429 } // namespace compiler
3457 } // namespace internal 3430 } // namespace internal
3458 } // namespace v8 3431 } // namespace v8
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