Subzero. ARM32. Fixes register aliasing bugs.

pydir/gen_arm32_reg_tables.py

 import os
 import sys
 
 class RegAliases(object):
   def __init__(self, AliasesStr):
     self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))
 
   def __str__(self):
     return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(
       AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))
@@ skipping 47 matching lines @@
     self.Encode = Encode
     if not AsmStr:
       AsmStr = '%s' % Name
     self.Features = RegFeatures(AsmStr=AsmStr, **Features)
 
   def __str__(self):
     return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name,
       Encode=self.Encode, Features=self.Features)
 
   def IsAnAliasOf(self, Other):
-    return self.Name in self.Features.Aliases().Aliases
+    return Other.Name in self.Features.Aliases().Aliases
 
 # Note: The following tables break the usual 80-col on purpose -- it is easier
 # to read the register tables if each register entry is contained on a single
 # line.
 GPRs = [
   Reg( 'r0',  0,   IsScratch=1, CCArg=1, IsInt=1,               Aliases= 'r0,  r0r1'),
   Reg( 'r1',  1,   IsScratch=1, CCArg=2, IsInt=1,               Aliases= 'r1,  r0r1'),
   Reg( 'r2',  2,   IsScratch=1, CCArg=3, IsInt=1,               Aliases= 'r2,  r2r3'),
   Reg( 'r3',  3,   IsScratch=1, CCArg=4, IsInt=1,               Aliases= 'r3,  r2r3'),
   Reg( 'r4',  4, IsPreserved=1,          IsInt=1,               Aliases= 'r4,  r4r5'),
@@ skipping 44 matching lines @@
   Reg('s21', 21, IsPreserved=1,           IsFP32=1, Aliases='s21, d10, q5'),
   Reg('s22', 22, IsPreserved=1,           IsFP32=1, Aliases='s22, d11, q5'),
   Reg('s23', 23, IsPreserved=1,           IsFP32=1, Aliases='s23, d11, q5'),
   Reg('s24', 24, IsPreserved=1,           IsFP32=1, Aliases='s24, d12, q6'),
   Reg('s25', 25, IsPreserved=1,           IsFP32=1, Aliases='s25, d12, q6'),
   Reg('s26', 26, IsPreserved=1,           IsFP32=1, Aliases='s26, d13, q6'),
   Reg('s27', 27, IsPreserved=1,           IsFP32=1, Aliases='s27, d13, q6'),
   Reg('s28', 28, IsPreserved=1,           IsFP32=1, Aliases='s28, d14, q7'),
   Reg('s29', 29, IsPreserved=1,           IsFP32=1, Aliases='s29, d14, q7'),
   Reg('s30', 30, IsPreserved=1,           IsFP32=1, Aliases='s30, d15, q7'),
-  Reg('s31', 31, IsPreserved=1,           IsFP32=1, Aliases='s31, d14, q7'),
+  Reg('s31', 31, IsPreserved=1,           IsFP32=1, Aliases='s31, d15, q7'),
 ]
 
 FP64 = [
   Reg( 'd0',  0,   IsScratch=1, CCArg=1, IsFP64=1, Aliases= 'd0,  q0,  s0,  s1'),
   Reg( 'd1',  1,   IsScratch=1, CCArg=2, IsFP64=1, Aliases= 'd1,  q0,  s2,  s3'),
   Reg( 'd2',  2,   IsScratch=1, CCArg=3, IsFP64=1, Aliases= 'd2,  q1,  s4,  s5'),
   Reg( 'd3',  3,   IsScratch=1, CCArg=4, IsFP64=1, Aliases= 'd3,  q1,  s6,  s7'),
   Reg( 'd4',  4,   IsScratch=1, CCArg=5, IsFP64=1, Aliases= 'd4,  q2,  s8,  s9'),
   Reg( 'd5',  5,   IsScratch=1, CCArg=6, IsFP64=1, Aliases= 'd5,  q2, s10, s11'),
   Reg( 'd6',  6,   IsScratch=1, CCArg=7, IsFP64=1, Aliases= 'd6,  q3, s12, s13'),
   Reg( 'd7',  7,   IsScratch=1, CCArg=8, IsFP64=1, Aliases= 'd7,  q3, s14, s15'),
   Reg( 'd8',  8, IsPreserved=1,          IsFP64=1, Aliases= 'd8,  q4, s16, s17'),
   Reg( 'd9',  9, IsPreserved=1,          IsFP64=1, Aliases= 'd9,  q4, s18, s19'),
   Reg('d10', 10, IsPreserved=1,          IsFP64=1, Aliases='d10,  q5, s20, s21'),
-  Reg('d11', 11, IsPreserved=1,          IsFP64=1, Aliases='d11,  q5, s22, s24'),
+  Reg('d11', 11, IsPreserved=1,          IsFP64=1, Aliases='d11,  q5, s22, s23'),
   Reg('d12', 12, IsPreserved=1,          IsFP64=1, Aliases='d12,  q6, s24, s25'),
   Reg('d13', 13, IsPreserved=1,          IsFP64=1, Aliases='d13,  q6, s26, s27'),
-  Reg('d14', 14, IsPreserved=1,          IsFP64=1, Aliases='d14,  q7, s28, s28'),
+  Reg('d14', 14, IsPreserved=1,          IsFP64=1, Aliases='d14,  q7, s28, s29'),
   Reg('d15', 15, IsPreserved=1,          IsFP64=1, Aliases='d15,  q7, s30, s31'),
   Reg('d16', 16,   IsScratch=1,          IsFP64=1, Aliases='d16,  q8'),
   Reg('d17', 17,   IsScratch=1,          IsFP64=1, Aliases='d17,  q8'),
   Reg('d18', 18,   IsScratch=1,          IsFP64=1, Aliases='d18,  q9'),
   Reg('d19', 19,   IsScratch=1,          IsFP64=1, Aliases='d19,  q9'),
   Reg('d20', 20,   IsScratch=1,          IsFP64=1, Aliases='d20, q10'),
   Reg('d21', 21,   IsScratch=1,          IsFP64=1, Aliases='d21, q10'),
   Reg('d22', 22,   IsScratch=1,          IsFP64=1, Aliases='d22, q11'),
   Reg('d23', 23,   IsScratch=1,          IsFP64=1, Aliases='d23, q11'),
   Reg('d24', 24,   IsScratch=1,          IsFP64=1, Aliases='d24, q12'),
@@ skipping 34 matching lines @@
 AllRegs = {}
 for _, RegClass in RegClasses:
   for Reg in RegClass:
     assert Reg.Name not in AllRegs
     AllRegs[Reg.Name] = Reg
 
 for _, RegClass in RegClasses:
   for Reg in RegClass:
     for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases:
       assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
-      assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
       assert (AllRegs[Alias].Features.LivesInGPR() ==
                  Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias])
       assert (AllRegs[Alias].Features.LivesInVFP() ==
                  Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])
 
 print ("// This file was auto generated by the {script} script.\n"
        "// Do not modify it: modify the script instead.\n"
        "\n"
        "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
        "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
  
 for Name, RegClass in RegClasses:
   print "#define REGARM32_%s_TABLE" % Name,
   for Reg in RegClass:
     print '\\\n  X({Reg})'.format(Reg=Reg),
   print '\n'
 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",