Subzero. Introduces a new LoweringContext::insert() method.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 998 matching lines @@
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
         Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
     if (!UseFramePointer) {
       // If we don't need a Frame Pointer, this alloca has a known offset to the
       // stack pointer. We don't need adjust the stack pointer, nor assign any
       // value to Dest, as Dest is rematerializable.
       assert(Dest->isRematerializable());
       FixedAllocaSizeBytes += Value;
-      Context.insert(InstFakeDef::create(Func, Dest));
+      Context.insert<InstFakeDef>(Dest);
     } else {
       _sub(esp, Ctx->getConstantInt32(Value));
     }
   } else {
     // Non-constant sizes need to be adjusted to the next highest multiple of
     // the required alignment at runtime.
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
@@ skipping 321 matching lines @@
     Context.insert(Label);
     _mov(DestLo, T_2);
     _mov(DestHi, T_3);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
   if (Dest->isRematerializable()) {
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeDef>(Dest);
     return;
   }
   Type Ty = Dest->getType();
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   if (Inst->isCommutative()) {
     uint32_t SwapCount = 0;
     if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1)) {
       std::swap(Src0, Src1);
       ++SwapCount;
@@ skipping 97 matching lines @@
       // The mul instruction cannot take an immediate operand.
       Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem);
       _mov(T_1, Src0Hi);
       _imul(T_1, Src1Lo);
       _mov(T_2, Src1Hi);
       _imul(T_2, Src0Lo);
       _mov(T_3, Src0Lo, Traits::RegisterSet::Reg_eax);
       _mul(T_4Lo, T_3, Src1Lo);
       // The mul instruction produces two dest variables, edx:eax. We create a
       // fake definition of edx to account for this.
-      Context.insert(InstFakeDef::create(Func, T_4Hi, T_4Lo));
+      Context.insert<InstFakeDef>(T_4Hi, T_4Lo);
       _mov(DestLo, T_4Lo);
       _add(T_4Hi, T_1);
       _add(T_4Hi, T_2);
       _mov(DestHi, T_4Hi);
     } break;
     case InstArithmetic::Shl:
     case InstArithmetic::Lshr:
     case InstArithmetic::Ashr:
       lowerShift64(Inst->getOp(), Src0Lo, Src0Hi, Src1Lo, DestLo, DestHi);
       break;
@@ skipping 414 matching lines @@
   case InstArithmetic::Frem:
     llvm::report_fatal_error("Helper call was expected");
     break;
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   if (Dest->isRematerializable()) {
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeDef>(Dest);
     return;
   }
   Operand *Src = Inst->getSrc(0);
   assert(Dest->getType() == Src->getType());
   lowerMove(Dest, Src, false);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerBr(const InstBr *Br) {
   if (Br->isUnconditional()) {
@@ skipping 445 matching lines @@
 
         Variable *T_Lo = nullptr, *T_Hi = nullptr;
         auto *SpillLo = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::Low);
         auto *SpillHi = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::High);
         _mov(T_Lo, loOperand(Src0));
         // Technically, the Spill is defined after the _store happens, but
         // SpillLo is considered a "use" of Spill so define Spill before it is
         // used.
-        Context.insert(InstFakeDef::create(Func, Spill));
+        Context.insert<InstFakeDef>(Spill);
         _store(T_Lo, SpillLo);
         _mov(T_Hi, hiOperand(Src0));
         _store(T_Hi, SpillHi);
         _movq(Dest, Spill);
       }
     } break;
     case IceType_v8i1: {
       llvm::report_fatal_error("Helper call was expected");
     } break;
     case IceType_v16i1: {
@@ skipping 52 matching lines @@
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElementR, T);
     } else { // Ty == IceType_f32
       // TODO(wala): _movss is only used here because _mov does not allow a
       // vector source and a scalar destination.  _mov should be able to be
       // used here.
       // _movss is a binary instruction, so the FakeDef is needed to keep the
       // live range analysis consistent.
-      Context.insert(InstFakeDef::create(Func, ExtractedElementR));
+      Context.insert<InstFakeDef>(ExtractedElementR);
       _movss(ExtractedElementR, T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
     // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
@@ skipping 415 matching lines @@
     switch (Condition) {
     default:
       llvm_unreachable("unexpected condition");
       break;
     case InstIcmp::Eq:
     case InstIcmp::Ule:
       // Mov Src0HiRM first, because it was legalized most recently, and will
       // sometimes avoid a move before the OR.
       _mov(Temp, Src0HiRM);
       _or(Temp, Src0LoRM);
-      Context.insert(InstFakeUse::create(Func, Temp));
+      Context.insert<InstFakeUse>(Temp);
       setccOrConsumer(Traits::Cond::Br_e, Dest, Consumer);
       return;
     case InstIcmp::Ne:
     case InstIcmp::Ugt:
       // Mov Src0HiRM first, because it was legalized most recently, and will
       // sometimes avoid a move before the OR.
       _mov(Temp, Src0HiRM);
       _or(Temp, Src0LoRM);
-      Context.insert(InstFakeUse::create(Func, Temp));
+      Context.insert<InstFakeUse>(Temp);
       setccOrConsumer(Traits::Cond::Br_ne, Dest, Consumer);
       return;
     case InstIcmp::Uge:
       movOrConsumer(true, Dest, Consumer);
       return;
     case InstIcmp::Ult:
       movOrConsumer(false, Dest, Consumer);
       return;
     case InstIcmp::Sgt:
       break;
@@ skipping 144 matching lines @@
   case InstArithmetic::Or:
     _mov(T, Src0);
     _or(T, Src1);
     break;
   }
 
   if (Consumer == nullptr) {
     llvm::report_fatal_error("Expected a consumer instruction");
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
-    Context.insert(InstFakeUse::create(Func, T));
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeUse>(T);
+    Context.insert<InstFakeDef>(Dest);
     _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   Operand *ElementToInsertNotLegalized = Inst->getSrc(1);
@@ skipping 208 matching lines @@
         // anyway, since this is x86-32 and integer arithmetic only happens on
         // 32-bit quantities.
         Variable *T = makeReg(IceType_f64);
         typename Traits::X86OperandMem *Addr =
             formMemoryOperand(Instr->getArg(0), IceType_f64);
         _movq(T, Addr);
         // Then cast the bits back out of the XMM register to the i64 Dest.
         auto *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
         lowerCast(Cast);
         // Make sure that the atomic load isn't elided when unused.
-        Context.insert(InstFakeUse::create(Func, Dest64On32->getLo()));
-        Context.insert(InstFakeUse::create(Func, Dest64On32->getHi()));
+        Context.insert<InstFakeUse>(Dest64On32->getLo());
+        Context.insert<InstFakeUse>(Dest64On32->getHi());
         return;
       }
     }
     auto *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
     lowerLoad(Load);
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
     // Since lowerLoad may fuse the load w/ an arithmetic instruction, insert
     // the FakeUse on the last-inserted instruction's dest.
-    Context.insert(
-        InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
+    Context.insert<InstFakeUse>(Context.getLastInserted()->getDest());
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)))) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
     lowerAtomicRMW(
         Instr->getDest(),
@@ skipping 518 matching lines @@
     }
     constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     _br(Traits::Cond::Br_ne, Label);
     if (!IsXchg8b) {
       // If Val is a variable, model the extended live range of Val through
       // the end of the loop, since it will be re-used by the loop.
       if (auto *ValVar = llvm::dyn_cast<Variable>(Val)) {
         auto *ValLo = llvm::cast<Variable>(loOperand(ValVar));
         auto *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
-        Context.insert(InstFakeUse::create(Func, ValLo));
-        Context.insert(InstFakeUse::create(Func, ValHi));
+        Context.insert<InstFakeUse>(ValLo);
+        Context.insert<InstFakeUse>(ValHi);
       }
     } else {
       // For xchg, the loop is slightly smaller and ebx/ecx are used.
-      Context.insert(InstFakeUse::create(Func, T_ebx));
-      Context.insert(InstFakeUse::create(Func, T_ecx));
+      Context.insert<InstFakeUse>(T_ebx);
+      Context.insert<InstFakeUse>(T_ecx);
     }
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
-      Context.insert(InstFakeUse::create(Func, Base));
+      Context.insert<InstFakeUse>(Base);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   int32_t Eax;
   switch (Ty) {
   default:
     llvm_unreachable("Bad type for atomicRMW");
   // fallthrough
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
     Eax = Traits::RegisterSet::Reg_ax;
     break;
   case IceType_i8:
     Eax = Traits::RegisterSet::Reg_al;
     break;
   }
   Variable *T_eax = makeReg(Ty, Eax);
   _mov(T_eax, Addr);
-  typename Traits::Insts::Label *Label =
-      Traits::Insts::Label::create(Func, this);
-  Context.insert(Label);
+  auto *Label = Context.insert<typename Traits::Insts::Label>(this);
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
   _br(Traits::Cond::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (auto *ValVar = llvm::dyn_cast<Variable>(Val)) {
-    Context.insert(InstFakeUse::create(Func, ValVar));
+    Context.insert<InstFakeUse>(ValVar);
   }
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
-    Context.insert(InstFakeUse::create(Func, Base));
+    Context.insert<InstFakeUse>(Base);
   _mov(Dest, T_eax);
 }
 
 /// Lowers count {trailing, leading} zeros intrinsic.
 ///
 /// We could do constant folding here, but that should have
 /// been done by the front-end/middle-end optimizations.
 template <class Machine>
 void TargetX86Base<Machine>::lowerCountZeros(bool Cttz, Type Ty, Variable *Dest,
                                              Operand *FirstVal,
@@ skipping 746 matching lines @@
   // something else.  We only care if it is Variable.
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
   if (Var == nullptr)
     return;
   // We use lowerStore() to copy out-args onto the stack.  This creates a memory
   // operand with the stack pointer as the base register.  Don't do bounds
   // checks on that.
   if (Var->getRegNum() == Traits::RegisterSet::Reg_esp)
     return;
 
-  typename Traits::Insts::Label *Label =
-      Traits::Insts::Label::create(Func, this);
+  auto *Label = Traits::Insts::Label::create(Func, this);
   _cmp(Opnd, Ctx->getConstantZero(IceType_i32));
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
@@ skipping 29 matching lines @@
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
     Addr = Traits::X86OperandMem::create(Func, Dest->getType(), Base, OffsetOp,
                                          Index, Shift, SegmentReg);
-    Context.insert(InstLoad::create(Func, Dest, Addr));
+    Context.insert<InstLoad>(Dest, Addr);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::randomlyInsertNop(float Probability,
                                                RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     _nop(RNGW(Traits::X86_NUM_NOP_VARIANTS));
   }
@@ skipping 43 matching lines @@
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerSelectMove(Variable *Dest,
                                              typename Traits::Cond::BrCond Cond,
                                              Operand *SrcT, Operand *SrcF) {
   Type DestTy = Dest->getType();
   if (typeWidthInBytes(DestTy) == 1 || isFloatingType(DestTy)) {
     // The cmov instruction doesn't allow 8-bit or FP operands, so we need
     // explicit control flow.
     // d=cmp e,f; a=d?b:c ==> cmp e,f; a=b; jne L1; a=c; L1:
-    typename Traits::Insts::Label *Label =
-        Traits::Insts::Label::create(Func, this);
+    auto *Label = Traits::Insts::Label::create(Func, this);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm);
     _mov(Dest, SrcT);
     _br(Cond, Label);
     SrcF = legalize(SrcF, Legal_Reg | Legal_Imm);
     _redefined(_mov(Dest, SrcF));
     Context.insert(Label);
     return;
   }
   // mov t, SrcF; cmov_cond t, SrcT; mov dest, t
   // But if SrcT is immediate, we might be able to do better, as the cmov
@@ skipping 221 matching lines @@
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
     Addr = Traits::X86OperandMem::create(Func, Data->getType(), Base, OffsetOp,
                                          Index, Shift, SegmentReg);
-    auto *NewStore = InstStore::create(Func, Data, Addr);
+    auto *NewStore = Context.insert<InstStore>(Data, Addr);
     if (Inst->getDest())
       NewStore->setRmwBeacon(Inst->getRmwBeacon());
-    Context.insert(NewStore);
   }
 }
 
 template <class Machine>
 Operand *TargetX86Base<Machine>::lowerCmpRange(Operand *Comparison,
                                                uint64_t Min, uint64_t Max) {
   // TODO(ascull): 64-bit should not reach here but only because it is not
   // implemented yet. This should be able to handle the 64-bit case.
   assert(Traits::Is64Bit || Comparison->getType() != IceType_i64);
   // Subtracting 0 is a nop so don't do it
@@ skipping 231 matching lines @@
   Type Ty = Dest->getType();
   Type ElementTy = typeElementType(Ty);
   SizeT NumElements = typeNumElements(Ty);
 
   Operand *T = Ctx->getConstantUndef(Ty);
   for (SizeT I = 0; I < NumElements; ++I) {
     Constant *Index = Ctx->getConstantInt32(I);
 
     // Extract the next two inputs.
     Variable *Op0 = Func->makeVariable(ElementTy);
-    Context.insert(InstExtractElement::create(Func, Op0, Src0, Index));
+    Context.insert<InstExtractElement>(Op0, Src0, Index);
     Variable *Op1 = Func->makeVariable(ElementTy);
-    Context.insert(InstExtractElement::create(Func, Op1, Src1, Index));
+    Context.insert<InstExtractElement>(Op1, Src1, Index);
 
     // Perform the arithmetic as a scalar operation.
     Variable *Res = Func->makeVariable(ElementTy);
-    auto *Arith = InstArithmetic::create(Func, Kind, Res, Op0, Op1);
-    Context.insert(Arith);
+    auto *Arith = Context.insert<InstArithmetic>(Kind, Res, Op0, Op1);
     // We might have created an operation that needed a helper call.
     genTargetHelperCallFor(Arith);
 
     // Insert the result into position.
     Variable *DestT = Func->makeVariable(Ty);
-    Context.insert(InstInsertElement::create(Func, DestT, T, Res, Index));
+    Context.insert<InstInsertElement>(DestT, T, Res, Index);
     T = DestT;
   }
 
-  Context.insert(InstAssign::create(Func, Dest, T));
+  Context.insert<InstAssign>(Dest, T);
 }
 
 /// The following pattern occurs often in lowered C and C++ code:
 ///
 ///   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
 ///   %cmp.ext = sext <n x i1> %cmp to <n x ty>
 ///
 /// We can eliminate the sext operation by copying the result of pcmpeqd,
 /// pcmpgtd, or cmpps (which produce sign extended results) to the result of the
 /// sext operation.
@@ skipping 270 matching lines @@
         break;
       case IceType_i16:
         assert(Src0->getType() == IceType_v16i1);
         HelperName = H_bitcast_16xi1_i16;
         break;
       case IceType_v8i1: {
         assert(Src0->getType() == IceType_i8);
         HelperName = H_bitcast_i8_8xi1;
         Variable *Src0AsI32 = Func->makeVariable(stackSlotType());
         // Arguments to functions are required to be at least 32 bits wide.
-        Context.insert(InstCast::create(Func, InstCast::Zext, Src0AsI32, Src0));
+        Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
         Src0 = Src0AsI32;
       } break;
       case IceType_v16i1: {
         assert(Src0->getType() == IceType_i16);
         HelperName = H_bitcast_i16_16xi1;
         Variable *Src0AsI32 = Func->makeVariable(stackSlotType());
         // Arguments to functions are required to be at least 32 bits wide.
-        Context.insert(InstCast::create(Func, InstCast::Zext, Src0AsI32, Src0));
+        Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
         Src0 = Src0AsI32;
       } break;
       }
     } break;
     }
     constexpr SizeT MaxSrcs = 1;
     InstCall *Call = makeHelperCall(HelperName, Dest, MaxSrcs);
     Call->addArg(Src0);
     StackArgumentsSize = getCallStackArgumentsSizeBytes(Call);
     Context.insert(Call);
@@ skipping 114 matching lines @@
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
   case IceType_i32:
   case IceType_i64:
     // Conservatively do "mov reg, 0" to avoid modifying FLAGS.
     _mov(Reg, Ctx->getConstantZero(Ty));
     break;
   case IceType_f32:
   case IceType_f64:
-    Context.insert(InstFakeDef::create(Func, Reg));
+    Context.insert<InstFakeDef>(Reg);
     _xorps(Reg, Reg);
     break;
   default:
     // All vector types use the same pxor instruction.
     assert(isVectorType(Ty));
-    Context.insert(InstFakeDef::create(Func, Reg));
+    Context.insert<InstFakeDef>(Reg);
     _pxor(Reg, Reg);
     break;
   }
   return Reg;
 }
 
 // There is no support for loading or emitting vector constants, so the vector
 // values returned from makeVectorOfZeros, makeVectorOfOnes, etc. are
 // initialized with register operations.
 //
 // TODO(wala): Add limited support for vector constants so that complex
 // initialization in registers is unnecessary.
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   return makeZeroedRegister(Ty, RegNum);
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfMinusOnes(Type Ty,
                                                         int32_t RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
-  Context.insert(InstFakeDef::create(Func, MinusOnes));
+  Context.insert<InstFakeDef>(MinusOnes);
   _pcmpeq(MinusOnes, MinusOnes);
   return MinusOnes;
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfOnes(Type Ty, int32_t RegNum) {
   Variable *Dest = makeVectorOfZeros(Ty, RegNum);
   Variable *MinusOne = makeVectorOfMinusOnes(Ty);
   _psub(Dest, MinusOne);
   return Dest;
@@ skipping 289 matching lines @@
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalizeUndef(Operand *From, int32_t RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register results
     // in less predictable code.
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
-    //     Context.insert(InstFakeDef::create(Func, Reg));
+    //     Context.insert<InstFakeDef>(Reg);
     // This is in order to ensure that the live range of Reg is not
     // overestimated.  If the constant being lowered is a 64 bit value, then
     // the result should be split and the lo and hi components will need to go
     // in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
@@ skipping 332 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H