Subzero. Introduces a new LoweringContext::insert() method.

src/IceTargetLoweringMIPS32.cpp

 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 370 matching lines @@
       Variable *RegisterArg = Func->makeVariable(Ty);
       auto *RegisterArg64On32 = llvm::cast<Variable64On32>(RegisterArg);
       if (BuildDefs::dump())
         RegisterArg64On32->setName(Func, "home_reg:" + Arg->getName(Func));
       RegisterArg64On32->initHiLo(Func);
       RegisterArg64On32->setIsArg();
       RegisterArg64On32->getLo()->setRegNum(RegLo);
       RegisterArg64On32->getHi()->setRegNum(RegHi);
       Arg->setIsArg(false);
       Args[I] = RegisterArg64On32;
-      Context.insert(InstAssign::create(Func, Arg, RegisterArg));
+      Context.insert<InstAssign>(Arg, RegisterArg);
       continue;
     } else {
       assert(Ty == IceType_i32);
       if (NumGPRRegsUsed >= MIPS32_MAX_GPR_ARG)
         continue;
       int32_t RegNum = RegMIPS32::Reg_A0 + NumGPRRegsUsed;
       ++NumGPRRegsUsed;
       Variable *RegisterArg = Func->makeVariable(Ty);
       if (BuildDefs::dump()) {
         RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
       }
       RegisterArg->setRegNum(RegNum);
       RegisterArg->setIsArg();
       Arg->setIsArg(false);
       Args[I] = RegisterArg;
-      Context.insert(InstAssign::create(Func, Arg, RegisterArg));
+      Context.insert<InstAssign>(Arg, RegisterArg);
     }
   }
 }
 
 Type TargetMIPS32::stackSlotType() { return IceType_i32; }
 
 void TargetMIPS32::addProlog(CfgNode *Node) {
   (void)Node;
   return;
   UnimplementedError(Func->getContext()->getFlags());
@@ skipping 108 matching lines @@
 }
 
 void TargetMIPS32::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   Operand *Src1 = legalizeUndef(Inst->getSrc(1));
   if (Dest->getType() == IceType_i64) {
     // TODO(reed kotler): fakedef needed for now until all cases are implemented
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
-    Context.insert(InstFakeDef::create(Func, DestLo));
-    Context.insert(InstFakeDef::create(Func, DestHi));
+    Context.insert<InstFakeDef>(DestLo);
+    Context.insert<InstFakeDef>(DestHi);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   if (isVectorType(Dest->getType())) {
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeDef>(Dest);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   // Dest->getType() is non-i64 scalar
   Variable *T = makeReg(Dest->getType());
   Variable *Src0R = legalizeToReg(Src0);
   Variable *Src1R = legalizeToReg(Src1);
   switch (Inst->getOp()) {
   case InstArithmetic::_num:
     break;
@@ skipping 42 matching lines @@
     break;
   case InstArithmetic::Fmul:
     break;
   case InstArithmetic::Fdiv:
     break;
   case InstArithmetic::Frem:
     break;
   }
   // TODO(reed kotler):
   // fakedef and fakeuse needed for now until all cases are implemented
-  Context.insert(InstFakeUse::create(Func, Src0R));
-  Context.insert(InstFakeUse::create(Func, Src1R));
-  Context.insert(InstFakeDef::create(Func, Dest));
+  Context.insert<InstFakeUse>(Src0R);
+  Context.insert<InstFakeUse>(Src1R);
+  Context.insert<InstFakeDef>(Dest);
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetMIPS32::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
     Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg);
@@ skipping 263 matching lines @@
       Operand *Src0F = legalize(Src0, Legal_Reg);
       Reg = makeReg(Src0F->getType(), RegMIPS32::Reg_V0);
       _mov(Reg, Src0F);
       break;
     }
     case IceType_i64: {
       Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToReg(loOperand(Src0), RegMIPS32::Reg_V0);
       Variable *R1 = legalizeToReg(hiOperand(Src0), RegMIPS32::Reg_V1);
       Reg = R0;
-      Context.insert(InstFakeUse::create(Func, R1));
+      Context.insert<InstFakeUse>(R1);
       break;
     }
 
     default:
       UnimplementedError(Func->getContext()->getFlags());
     }
   }
   _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg);
 }
 
@@ skipping 113 matching lines @@
   assert(Allowed & Legal_Reg);
   // Go through the various types of operands:
   // OperandMIPS32Mem, Constant, and Variable.
   // Given the above assertion, if type of operand is not legal
   // (e.g., OperandMIPS32Mem and !Legal_Mem), we can always copy
   // to a register.
   if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) {
     (void)C;
     // TODO(reed kotler): complete this case for proper implementation
     Variable *Reg = makeReg(Ty, RegNum);
-    Context.insert(InstFakeDef::create(Func, Reg));
+    Context.insert<InstFakeDef>(Reg);
     return Reg;
   } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) {
     uint32_t Value = static_cast<uint32_t>(C32->getValue());
     // Check if the immediate will fit in a Flexible second operand,
     // if a Flexible second operand is allowed. We need to know the exact
     // value, so that rules out relocatable constants.
     // Also try the inverse and use MVN if possible.
     // Do a movw/movt to a register.
     Variable *Reg;
     if (RegNum == Variable::NoRegister)
@@ skipping 40 matching lines @@
       << "nomicromips\n";
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 llvm::SmallBitVector TargetMIPS32::ScratchRegs;
 
 } // end of namespace Ice