Subzero. Introduces a new LoweringContext::insert() method.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 339 matching lines @@
       case InstArithmetic::Urem:
         TargetHelper = Ctx->getConstantExternSym(H_urem_i64);
         break;
       case InstArithmetic::Srem:
         TargetHelper = Ctx->getConstantExternSym(H_srem_i64);
         break;
       }
       assert(TargetHelper != nullptr);
       ARM32HelpersPreamble[TargetHelper] = &TargetARM32::preambleDivRem;
       constexpr SizeT MaxArgs = 2;
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(Instr->getSrc(0));
       Call->addArg(Instr->getSrc(1));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case IceType_i32:
     case IceType_i16:
     case IceType_i8: {
       const bool HasHWDiv = hasCPUFeature(TargetARM32Features::HWDivArm);
       InstCast::OpKind CastKind;
       Operand *TargetHelper;
       switch (Op) {
@@ skipping 26 matching lines @@
         // the following assert will have to be modified.
         assert(HasHWDiv);
         return;
       }
       Operand *Src0 = Instr->getSrc(0);
       Operand *Src1 = Instr->getSrc(1);
       if (DestTy != IceType_i32) {
         // Src0 and Src1 have to be zero-, or signed-extended to i32. For Src0,
         // we just insert a InstCast right before the call to the helper.
         Variable *Src0_32 = Func->makeVariable(IceType_i32);
-        Context.insert(InstCast::create(Func, CastKind, Src0_32, Src0));
+        Context.insert<InstCast>(CastKind, Src0_32, Src0);
         Src0 = Src0_32;
 
         // For extending Src1, we will just insert an InstCast if Src1 is not a
         // Constant. If it is, then we extend it here, and not during program
         // runtime. This allows preambleDivRem to optimize-out the div-by-0
         // check.
         if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
           const int32_t ShAmt = (DestTy == IceType_i16) ? 16 : 24;
           int32_t NewC = C->getValue();
           if (CastKind == InstCast::Zext) {
             NewC &= ~(0x80000000l >> ShAmt);
           } else {
             NewC = (NewC << ShAmt) >> ShAmt;
           }
           Src1 = Ctx->getConstantInt32(NewC);
         } else {
           Variable *Src1_32 = Func->makeVariable(IceType_i32);
-          Context.insert(InstCast::create(Func, CastKind, Src1_32, Src1));
+          Context.insert<InstCast>(CastKind, Src1_32, Src1);
           Src1 = Src1_32;
         }
       }
       assert(TargetHelper != nullptr);
       ARM32HelpersPreamble[TargetHelper] = &TargetARM32::preambleDivRem;
       constexpr SizeT MaxArgs = 2;
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       assert(Src0->getType() == IceType_i32);
       Call->addArg(Src0);
       assert(Src1->getType() == IceType_i32);
       Call->addArg(Src1);
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case IceType_f64:
     case IceType_f32: {
       if (Op != InstArithmetic::Frem) {
         return;
       }
       constexpr SizeT MaxArgs = 2;
       Operand *TargetHelper = Ctx->getConstantExternSym(
           DestTy == IceType_f32 ? H_frem_f32 : H_frem_f64);
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(Instr->getSrc(0));
       Call->addArg(Instr->getSrc(1));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   case Inst::Cast: {
     Variable *Dest = Instr->getDest();
     Operand *Src0 = Instr->getSrc(0);
     const Type DestTy = Dest->getType();
     const InstCast::OpKind CastKind =
         llvm::cast<InstCast>(Instr)->getCastKind();
     switch (CastKind) {
     default:
       return;
     case InstCast::Fptosi:
     case InstCast::Fptoui: {
       if (DestTy != IceType_i64) {
         return;
       }
       const bool DestIsSigned = CastKind == InstCast::Fptosi;
       const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType());
       Operand *TargetHelper = Ctx->getConstantExternSym(
           Src0IsF32 ? (DestIsSigned ? H_fptosi_f32_i64 : H_fptoui_f32_i64)
                     : (DestIsSigned ? H_fptosi_f64_i64 : H_fptoui_f64_i64));
       static constexpr SizeT MaxArgs = 1;
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case InstCast::Sitofp:
     case InstCast::Uitofp: {
       if (Src0->getType() != IceType_i64) {
         return;
       }
       const bool SourceIsSigned = CastKind == InstCast::Sitofp;
       const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
       Operand *TargetHelper = Ctx->getConstantExternSym(
           DestIsF32 ? (SourceIsSigned ? H_sitofp_i64_f32 : H_uitofp_i64_f32)
                     : (SourceIsSigned ? H_sitofp_i64_f64 : H_uitofp_i64_f64));
       static constexpr SizeT MaxArgs = 1;
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   case Inst::IntrinsicCall: {
     Variable *Dest = Instr->getDest();
     auto *IntrinsicCall = llvm::cast<InstIntrinsicCall>(Instr);
     Intrinsics::IntrinsicID ID = IntrinsicCall->getIntrinsicInfo().ID;
     switch (ID) {
     default:
       return;
     case Intrinsics::Ctpop: {
       Operand *Src0 = IntrinsicCall->getArg(0);
       Operand *TargetHelper = Ctx->getConstantExternSym(
           isInt32Asserting32Or64(Src0->getType()) ? H_call_ctpop_i32
                                                   : H_call_ctpop_i64);
       static constexpr SizeT MaxArgs = 1;
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
-      Context.insert(Call);
       Instr->setDeleted();
       if (Src0->getType() == IceType_i64) {
         ARM32HelpersPostamble[TargetHelper] = &TargetARM32::postambleCtpop64;
       }
       return;
     }
     case Intrinsics::Longjmp: {
       static constexpr SizeT MaxArgs = 2;
       static constexpr Variable *NoDest = nullptr;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_longjmp);
-      auto *Call = InstCall::create(Func, MaxArgs, NoDest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memcpy: {
       // In the future, we could potentially emit an inline memcpy/memset, etc.
       // for intrinsic calls w/ a known length.
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memcpy);
-      auto *Call = InstCall::create(Func, MaxArgs, NoDest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
       Call->addArg(IntrinsicCall->getArg(2));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memmove: {
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memmove);
-      auto *Call = InstCall::create(Func, MaxArgs, NoDest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
       Call->addArg(IntrinsicCall->getArg(2));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memset: {
       // The value operand needs to be extended to a stack slot size because the
       // PNaCl ABI requires arguments to be at least 32 bits wide.
       Operand *ValOp = IntrinsicCall->getArg(1);
       assert(ValOp->getType() == IceType_i8);
       Variable *ValExt = Func->makeVariable(stackSlotType());
-      Context.insert(InstCast::create(Func, InstCast::Zext, ValExt, ValOp));
+      Context.insert<InstCast>(InstCast::Zext, ValExt, ValOp);
 
       // Technically, ARM has its own __aeabi_memset, but we can use plain
       // memset too. The value and size argument need to be flipped if we ever
       // decide to use __aeabi_memset.
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memset);
-      auto *Call = InstCall::create(Func, MaxArgs, NoDest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(ValExt);
       Call->addArg(IntrinsicCall->getArg(2));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::NaClReadTP: {
       if (NeedSandboxing) {
         return;
       }
       static constexpr SizeT MaxArgs = 0;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_read_tp);
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
-      Context.insert(Call);
+      Context.insert<InstCall>(MaxArgs, Dest, TargetHelper, NoTailCall,
+                               IsTargetHelperCall);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Setjmp: {
       static constexpr SizeT MaxArgs = 1;
       Operand *TargetHelper = Ctx->getConstantExternSym(H_call_setjmp);
-      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
-                                    NoTailCall, IsTargetHelperCall);
+      auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
+                                            NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
-      Context.insert(Call);
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   }
 }
 
 void TargetARM32::findMaxStackOutArgsSize() {
@@ skipping 395 matching lines @@
     default: { RegisterArg->setRegNum(RegNum); } break;
     case IceType_i64: {
       auto *RegisterArg64 = llvm::cast<Variable64On32>(RegisterArg);
       RegisterArg64->initHiLo(Func);
       RegisterArg64->getLo()->setRegNum(
           RegARM32::getI64PairFirstGPRNum(RegNum));
       RegisterArg64->getHi()->setRegNum(
           RegARM32::getI64PairSecondGPRNum(RegNum));
     } break;
     }
-    Context.insert(InstAssign::create(Func, Arg, RegisterArg));
+    Context.insert<InstAssign>(Arg, RegisterArg);
   }
 }
 
 // Helper function for addProlog().
 //
 // This assumes Arg is an argument passed on the stack. This sets the frame
 // offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
 // I64 arg that has been split into Lo and Hi components, it calls itself
 // recursively on the components, taking care to handle Lo first because of the
 // little-endian architecture. Lastly, this function generates an instruction
@@ skipping 180 matching lines @@
     _push(PreservedSRegs);
   if (!PreservedGPRs.empty())
     _push(PreservedGPRs);
 
   // Generate "mov FP, SP" if needed.
   if (UsesFramePointer) {
     Variable *FP = getPhysicalRegister(RegARM32::Reg_fp);
     Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     _mov(FP, SP);
     // Keep FP live for late-stage liveness analysis (e.g. asm-verbose mode).
-    Context.insert(InstFakeUse::create(Func, FP));
+    Context.insert<InstFakeUse>(FP);
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of the region
   // after the preserved registers and before the spill areas.
   // LocalsSlotsPaddingBytes is the amount of padding between the globals and
   // locals area if they are separate.
   assert(SpillAreaAlignmentBytes <= ARM32_STACK_ALIGNMENT_BYTES);
   assert(LocalsSlotsAlignmentBytes <= SpillAreaAlignmentBytes);
   uint32_t SpillAreaPaddingBytes = 0;
   uint32_t LocalsSlotsPaddingBytes = 0;
@@ skipping 108 matching lines @@
   --InsertPoint;
   Context.init(Node);
   Context.setInsertPoint(InsertPoint);
 
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   if (UsesFramePointer) {
     Variable *FP = getPhysicalRegister(RegARM32::Reg_fp);
     // For late-stage liveness analysis (e.g. asm-verbose mode), adding a fake
     // use of SP before the assignment of SP=FP keeps previous SP adjustments
     // from being dead-code eliminated.
-    Context.insert(InstFakeUse::create(Func, SP));
+    Context.insert<InstFakeUse>(SP);
     Sandboxer(this).reset_sp(FP);
   } else {
     // add SP, SpillAreaSizeBytes
     if (SpillAreaSizeBytes) {
       // Use the scratch register if needed to legalize the immediate.
       Operand *AddAmount =
           legalize(Ctx->getConstantInt32(SpillAreaSizeBytes),
                    Legal_Reg | Legal_Flex, getReservedTmpReg());
       Sandboxer(this).add_sp(AddAmount);
     }
@@ skipping 143 matching lines @@
   if (!Dest->hasReg()) {
     auto *SrcR = llvm::cast<Variable>(Src);
     assert(SrcR->hasReg());
     assert(!SrcR->isRematerializable());
     const int32_t Offset = Dest->getStackOffset();
     // This is a _mov(Mem(), Variable), i.e., a store.
     TargetARM32::Sandboxer(Target)
         .str(SrcR, createMemOperand(DestTy, StackOrFrameReg, Offset),
              MovInstr->getPredicate());
     // _str() does not have a Dest, so we add a fake-def(Dest).
-    Target->Context.insert(InstFakeDef::create(Target->Func, Dest));
+    Target->Context.insert<InstFakeDef>(Dest);
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->isRematerializable()) {
       // This is equivalent to an x86 _lea(RematOffset(%esp/%ebp), Variable).
 
       // ExtraOffset is only needed for frame-pointer based frames as we have
       // to account for spill storage.
       const int32_t ExtraOffset =
           (static_cast<SizeT>(Var->getRegNum()) == Target->getFrameReg())
               ? Target->getFrameFixedAllocaOffset()
@@ skipping 354 matching lines @@
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
         Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
     // Constant size alloca.
     if (!UseFramePointer) {
       // If we don't need a Frame Pointer, this alloca has a known offset to the
       // stack pointer. We don't need adjust the stack pointer, nor assign any
       // value to Dest, as Dest is rematerializable.
       assert(Dest->isRematerializable());
       FixedAllocaSizeBytes += Value;
-      Context.insert(InstFakeDef::create(Func, Dest));
+      Context.insert<InstFakeDef>(Dest);
       return;
     }
 
     // If a frame pointer is required, then we need to store the alloca'd result
     // in Dest.
     Operand *SubAmountRF =
         legalize(Ctx->getConstantInt32(Value), Legal_Reg | Legal_Flex);
     Sandboxer(this).sub_sp(SubAmountRF);
   } else {
     // Non-constant sizes need to be adjusted to the next highest multiple of
@@ skipping 24 matching lines @@
     return;
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm::report_fatal_error("Unexpected type");
   case IceType_i8:
   case IceType_i16: {
     Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty));
     Variable *T = makeReg(IceType_i32);
     _lsls(T, SrcLoReg, ShAmtImm);
-    Context.insert(InstFakeUse::create(Func, T));
+    Context.insert<InstFakeUse>(T);
   } break;
   case IceType_i32: {
     _tst(SrcLoReg, SrcLoReg);
     break;
   }
   case IceType_i64: {
     Variable *T = makeReg(IceType_i32);
     _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex));
     // T isn't going to be used, but we need the side-effect of setting flags
     // from this operation.
-    Context.insert(InstFakeUse::create(Func, T));
+    Context.insert<InstFakeUse>(T);
   }
   }
   auto *Label = InstARM32Label::create(Func, this);
   _br(Label, CondARM32::NE);
   _trap();
   Context.insert(Label);
 }
 
 void TargetARM32::lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R,
                                Operand *Src1, ExtInstr ExtFunc,
@@ skipping 735 matching lines @@
 
   return Src == 0;
 }
 } // end of namespace StrengthReduction
 } // end of anonymous namespace
 
 void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
   Variable *Dest = Instr->getDest();
 
   if (Dest->isRematerializable()) {
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeDef>(Dest);
     return;
   }
 
   Type DestTy = Dest->getType();
   if (DestTy == IceType_i1) {
     lowerInt1Arithmetic(Instr);
     return;
   }
 
   Operand *Src0 = legalizeUndef(Instr->getSrc(0));
   Operand *Src1 = legalizeUndef(Instr->getSrc(1));
   if (DestTy == IceType_i64) {
     lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1);
     return;
   }
 
   if (isVectorType(DestTy)) {
     // Add a fake def to keep liveness consistent in the meantime.
     Variable *T = makeReg(DestTy);
-    Context.insert(InstFakeDef::create(Func, T));
+    Context.insert<InstFakeDef>(T);
     _mov(Dest, T);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 
   // DestTy is a non-i64 scalar.
   Variable *T = makeReg(DestTy);
 
   // * Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
@@ skipping 311 matching lines @@
     llvm::report_fatal_error(
         "Floating point arith should have been handled earlier.");
     return;
   }
 }
 
 void TargetARM32::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
 
   if (Dest->isRematerializable()) {
-    Context.insert(InstFakeDef::create(Func, Dest));
+    Context.insert<InstFakeDef>(Dest);
     return;
   }
 
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
 
     Variable *T_Lo = makeReg(IceType_i32);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
@@ skipping 283 matching lines @@
   // Allow ConstantRelocatable to be left alone as a direct call, but force
   // other constants like ConstantInteger32 to be in a register and make it an
   // indirect call.
   if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
     CallTarget = legalize(CallTarget, Legal_Reg);
   }
 
   // Copy arguments to be passed in registers to the appropriate registers.
   for (auto &FPArg : FPArgs) {
     Variable *Reg = legalizeToReg(FPArg.first, FPArg.second);
-    Context.insert(InstFakeUse::create(Func, Reg));
+    Context.insert<InstFakeUse>(Reg);
   }
   for (auto &GPRArg : GPRArgs) {
     Variable *Reg = legalizeToReg(GPRArg.first, GPRArg.second);
     // Generate a FakeUse of register arguments so that they do not get dead
     // code eliminated as a result of the FakeKill of scratch registers after
     // the call.
-    Context.insert(InstFakeUse::create(Func, Reg));
+    Context.insert<InstFakeUse>(Reg);
   }
 
   InstARM32Call *NewCall =
       Sandboxer(this, InstBundleLock::Opt_AlignToEnd).bl(ReturnReg, CallTarget);
 
   if (ReturnRegHi)
-    Context.insert(InstFakeDef::create(Func, ReturnRegHi));
+    Context.insert<InstFakeDef>(ReturnRegHi);
 
   // Insert a register-kill pseudo instruction.
-  Context.insert(InstFakeKill::create(Func, NewCall));
+  Context.insert<InstFakeKill>(NewCall);
 
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
-    Inst *FakeUse = InstFakeUse::create(Func, ReturnReg);
-    Context.insert(FakeUse);
+    Context.insert<InstFakeUse>(ReturnReg);
   }
 
   if (Dest != nullptr) {
     // Assign the result of the call to Dest.
     if (ReturnReg != nullptr) {
       if (ReturnRegHi) {
         auto *Dest64On32 = llvm::cast<Variable64On32>(Dest);
         Variable *DestLo = Dest64On32->getLo();
         Variable *DestHi = Dest64On32->getHi();
         _mov(DestLo, ReturnReg);
@@ skipping 30 matching lines @@
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
@@ skipping 27 matching lines @@
       Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1);
       Variable *T = makeReg(Dest->getType());
       lowerInt1ForSelect(T, Src0, _m1, _0);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Operand *_0 =
           legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
 
@@ skipping 35 matching lines @@
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
     } else {
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       // t1 = trunc Src0RF; Dest = t1
       Variable *T = makeReg(Dest->getType());
       _mov(T, Src0RF);
       if (Dest->getType() == IceType_i1)
         _and(T, T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Fptrunc:
   case InstCast::Fpext: {
     // fptrunc: dest.f32 = fptrunc src0.fp64
     // fpext: dest.f64 = fptrunc src0.fp32
     const bool IsTrunc = CastKind == InstCast::Fptrunc;
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
     assert(Dest->getType() == (IsTrunc ? IceType_f32 : IceType_f64));
     assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32));
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T = makeReg(Dest->getType());
     _vcvt(T, Src0R, IsTrunc ? InstARM32Vcvt::D2s : InstARM32Vcvt::S2d);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
   case InstCast::Fptoui: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
 
     const bool DestIsSigned = CastKind == InstCast::Fptosi;
     const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType());
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("fp-to-i64 should have been pre-lowered.");
     }
@@ skipping 18 matching lines @@
       lowerCast(InstCast::create(Func, InstCast::Trunc, T_1, T));
       T = T_1;
     }
     _mov(Dest, T);
     break;
   }
   case InstCast::Sitofp:
   case InstCast::Uitofp: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
     const bool SourceIsSigned = CastKind == InstCast::Sitofp;
     const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
     if (Src0->getType() == IceType_i64) {
       llvm::report_fatal_error("i64-to-fp should have been pre-lowered.");
     }
     // sitofp:
@@ skipping 56 matching lines @@
     case IceType_i64: {
       // t0, t1 <- src0
       // dest[31..0]  = t0
       // dest[63..32] = t1
       assert(Src0->getType() == IceType_f64);
       auto *T = llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       T->initHiLo(Func);
       configureBitcastTemporary(T);
       Variable *Src0R = legalizeToReg(Src0);
       _mov(T, Src0R);
-      Context.insert(InstFakeUse::create(Func, T->getHi()));
-      Context.insert(InstFakeUse::create(Func, T->getLo()));
+      Context.insert<InstFakeUse>(T->getHi());
+      Context.insert<InstFakeUse>(T->getLo());
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_f64: {
       // T0 <- lo(src)
       // T1 <- hi(src)
       // vmov T2, T0, T1
       // Dest <- T2
       assert(Src0->getType() == IceType_i64);
       Variable *T = makeReg(DestType);
       auto *Src64 = llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       Src64->initHiLo(Func);
       configureBitcastTemporary(Src64);
       lowerAssign(InstAssign::create(Func, Src64, Src0));
       _mov(T, Src64);
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v8i16:
     case IceType_v16i8:
     case IceType_v4f32:
     case IceType_v4i32: {
       // avoid liveness errors
       Variable *T = makeReg(DestType);
-      Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
+      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
       break;
     }
     }
     break;
   }
   }
 }
 
 void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestType = Dest->getType();
   Variable *T = makeReg(DestType);
-  Context.insert(InstFakeDef::create(Func, T));
+  Context.insert<InstFakeDef>(T);
   _mov(Dest, T);
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 namespace {
 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering
 // (and naming).
 enum {
 #define X(val, CC0, CC1) _fcmp_ll_##val,
   FCMPARM32_TABLE
@@ skipping 61 matching lines @@
     assert(Condition < llvm::array_lengthof(TableFcmp));
     return CondWhenTrue(TableFcmp[Condition].CC0, TableFcmp[Condition].CC1);
   }
   }
 }
 
 void TargetARM32::lowerFcmp(const InstFcmp *Instr) {
   Variable *Dest = Instr->getDest();
   if (isVectorType(Dest->getType())) {
     Variable *T = makeReg(Dest->getType());
-    Context.insert(InstFakeDef::create(Func, T));
+    Context.insert<InstFakeDef>(T);
     _mov(Dest, T);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 
   Variable *T = makeReg(IceType_i1);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
 
@@ skipping 37 matching lines @@
   if (SrcsLo.hasConstOperand()) {
     const uint32_t ValueLo = SrcsLo.getConstantValue();
     const uint32_t ValueHi = SrcsHi.getConstantValue();
     const uint64_t Value = (static_cast<uint64_t>(ValueHi) << 32) | ValueLo;
     if ((Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) &&
         Value == 0) {
       Variable *T = makeReg(IceType_i32);
       Variable *Src0LoR = SrcsLo.src0R(this);
       Variable *Src0HiR = SrcsHi.src0R(this);
       _orrs(T, Src0LoR, Src0HiR);
-      Context.insert(InstFakeUse::create(Func, T));
+      Context.insert<InstFakeUse>(T);
       return CondWhenTrue(TableIcmp64[Index].C1);
     }
 
     Variable *Src0RLo = SrcsLo.src0R(this);
     Variable *Src0RHi = SrcsHi.src0R(this);
     Operand *Src1RFLo = SrcsLo.src1RF(this);
     Operand *Src1RFHi = ValueLo == ValueHi ? Src1RFLo : SrcsHi.src1RF(this);
 
     const bool UseRsb = TableIcmp64[Index].Swapped != SrcsLo.swappedOperands();
 
     if (UseRsb) {
       if (TableIcmp64[Index].IsSigned) {
         Variable *T = makeReg(IceType_i32);
         _rsbs(T, Src0RLo, Src1RFLo);
-        Context.insert(InstFakeUse::create(Func, T));
+        Context.insert<InstFakeUse>(T);
 
         T = makeReg(IceType_i32);
         _rscs(T, Src0RHi, Src1RFHi);
         // We need to add a FakeUse here because liveness gets mad at us (Def
         // without Use.) Note that flag-setting instructions are considered to
         // have side effects and, therefore, are not DCE'ed.
-        Context.insert(InstFakeUse::create(Func, T));
+        Context.insert<InstFakeUse>(T);
       } else {
         Variable *T = makeReg(IceType_i32);
         _rsbs(T, Src0RHi, Src1RFHi);
-        Context.insert(InstFakeUse::create(Func, T));
+        Context.insert<InstFakeUse>(T);
 
         T = makeReg(IceType_i32);
         _rsbs(T, Src0RLo, Src1RFLo, CondARM32::EQ);
-        Context.insert(InstFakeUse::create(Func, T));
+        Context.insert<InstFakeUse>(T);
       }
     } else {
       if (TableIcmp64[Index].IsSigned) {
         _cmp(Src0RLo, Src1RFLo);
         Variable *T = makeReg(IceType_i32);
         _sbcs(T, Src0RHi, Src1RFHi);
-        Context.insert(InstFakeUse::create(Func, T));
+        Context.insert<InstFakeUse>(T);
       } else {
         _cmp(Src0RHi, Src1RFHi);
         _cmp(Src0RLo, Src1RFLo, CondARM32::EQ);
       }
     }
 
     return CondWhenTrue(TableIcmp64[Index].C1);
   }
 
   Variable *Src0RLo, *Src0RHi;
@@ skipping 38 matching lines @@
   // longer sequence.
   //
   // So, we are going with the GCC version since it's usually better (except
   // perhaps for eq/ne). We could revisit special-casing eq/ne later.
   if (TableIcmp64[Index].IsSigned) {
     Variable *ScratchReg = makeReg(IceType_i32);
     _cmp(Src0RLo, Src1RFLo);
     _sbcs(ScratchReg, Src0RHi, Src1RFHi);
     // ScratchReg isn't going to be used, but we need the side-effect of
     // setting flags from this operation.
-    Context.insert(InstFakeUse::create(Func, ScratchReg));
+    Context.insert<InstFakeUse>(ScratchReg);
   } else {
     _cmp(Src0RHi, Src1RFHi);
     _cmp(Src0RLo, Src1RFLo, CondARM32::EQ);
   }
   return CondWhenTrue(TableIcmp64[Index].C1);
 }
 
 TargetARM32::CondWhenTrue
 TargetARM32::lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                 Operand *Src1) {
@@ skipping 19 matching lines @@
     _cmn(Src0R, Src1F);
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   Operand *Src1RF = Srcs.src1RF(this);
   if (!Srcs.swappedOperands()) {
     _cmp(Src0R, Src1RF);
   } else {
     Variable *T = makeReg(IceType_i32);
     _rsbs(T, Src0R, Src1RF);
-    Context.insert(InstFakeUse::create(Func, T));
+    Context.insert<InstFakeUse>(T);
   }
   return CondWhenTrue(getIcmp32Mapping(Condition));
 }
 
 TargetARM32::CondWhenTrue
 TargetARM32::lowerInt8AndInt16IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                        Operand *Src1) {
   Int32Operands Srcs(Src0, Src1);
   const int32_t ShAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShAmt >= 0);
 
   if (!Srcs.hasConstOperand()) {
     Variable *Src0R = makeReg(IceType_i32);
     Operand *ShAmtImm = shAmtImm(ShAmt);
     _lsl(Src0R, legalizeToReg(Src0), ShAmtImm);
 
     Variable *Src1R = legalizeToReg(Src1);
     auto *Src1F = OperandARM32FlexReg::create(Func, IceType_i32, Src1R,
                                               OperandARM32::LSL, ShAmtImm);
     _cmp(Src0R, Src1F);
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   const int32_t Value = Srcs.getConstantValue();
   if ((Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) && Value == 0) {
     Operand *ShAmtImm = shAmtImm(ShAmt);
     Variable *T = makeReg(IceType_i32);
     _lsls(T, Srcs.src0R(this), ShAmtImm);
-    Context.insert(InstFakeUse::create(Func, T));
+    Context.insert<InstFakeUse>(T);
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   Variable *ConstR = makeReg(IceType_i32);
   _mov(ConstR,
        legalize(Ctx->getConstantInt32(Value << ShAmt), Legal_Reg | Legal_Flex));
   Operand *NonConstF = OperandARM32FlexReg::create(
       Func, IceType_i32, Srcs.src0R(this), OperandARM32::LSL,
       Ctx->getConstantInt32(ShAmt));
 
   if (Srcs.swappedOperands()) {
     _cmp(ConstR, NonConstF);
   } else {
     Variable *T = makeReg(IceType_i32);
     _rsbs(T, ConstR, NonConstF);
-    Context.insert(InstFakeUse::create(Func, T));
+    Context.insert<InstFakeUse>(T);
   }
   return CondWhenTrue(getIcmp32Mapping(Condition));
 }
 
 TargetARM32::CondWhenTrue TargetARM32::lowerIcmpCond(const InstIcmp *Inst) {
   assert(Inst->getSrc(0)->getType() != IceType_i1);
   assert(Inst->getSrc(1)->getType() != IceType_i1);
 
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   Operand *Src1 = legalizeUndef(Inst->getSrc(1));
@@ skipping 39 matching lines @@
   case IceType_i64:
     return lowerInt64IcmpCond(Condition, Src0, Src1);
   }
 }
 
 void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
   Variable *Dest = Inst->getDest();
 
   if (isVectorType(Dest->getType())) {
     Variable *T = makeReg(Dest->getType());
-    Context.insert(InstFakeDef::create(Func, T));
+    Context.insert<InstFakeDef>(T);
     _mov(Dest, T);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Variable *T = makeReg(IceType_i1);
 
@@ skipping 73 matching lines @@
     ValueReg = makeReg(DestTy);
     ValueHiReg = nullptr;
     ValueLoReg = ValueReg;
 
     TmpReg = makeReg(DestTy);
     TmpHiReg = nullptr;
     TmpLoReg = TmpReg;
   }
 
   if (DestTy == IceType_i64) {
-    Context.insert(InstFakeDef::create(Func, Value));
+    Context.insert<InstFakeDef>(Value);
   }
   lowerAssign(InstAssign::create(Func, Value, Val));
 
   Variable *PtrVar = Func->makeVariable(IceType_i32);
   lowerAssign(InstAssign::create(Func, PtrVar, Ptr));
 
   _dmb();
   Context.insert(Retry);
   Mem = formMemoryOperand(PtrVar, DestTy);
   if (DestTy == IceType_i64) {
-    Context.insert(InstFakeDef::create(Func, ValueReg, Value));
+    Context.insert<InstFakeDef>(ValueReg, Value);
   }
   lowerAssign(InstAssign::create(Func, ValueReg, Value));
   if (DestTy == IceType_i8 || DestTy == IceType_i16) {
     _uxt(ValueReg, ValueReg);
   }
   _ldrex(PtrContentsReg, Mem);
 
   if (DestTy == IceType_i64) {
-    Context.insert(InstFakeDef::create(Func, TmpReg, ValueReg));
+    Context.insert<InstFakeDef>(TmpReg, ValueReg);
   }
   switch (Operation) {
   default:
     Func->setError("Unknown AtomicRMW operation");
     return;
   case Intrinsics::AtomicAdd:
     if (DestTy == IceType_i64) {
       _adds(TmpLoReg, PtrContentsLoReg, ValueLoReg);
       _adc(TmpHiReg, PtrContentsHiReg, ValueHiReg);
     } else {
@@ skipping 33 matching lines @@
     }
     break;
   }
   _strex(Success, TmpReg, Mem);
   _cmp(Success, _0);
   _br(Retry, CondARM32::NE);
 
   // The following fake-uses ensure that Subzero will not clobber them in the
   // load-linked/store-conditional loop above. We might have to spill them, but
   // spilling is preferable over incorrect behavior.
-  Context.insert(InstFakeUse::create(Func, PtrVar));
+  Context.insert<InstFakeUse>(PtrVar);
   if (auto *Value64 = llvm::dyn_cast<Variable64On32>(Value)) {
-    Context.insert(InstFakeUse::create(Func, Value64->getHi()));
-    Context.insert(InstFakeUse::create(Func, Value64->getLo()));
+    Context.insert<InstFakeUse>(Value64->getHi());
+    Context.insert<InstFakeUse>(Value64->getLo());
   } else {
-    Context.insert(InstFakeUse::create(Func, Value));
+    Context.insert<InstFakeUse>(Value);
   }
   _dmb();
   if (DestTy == IceType_i8 || DestTy == IceType_i16) {
     _uxt(PtrContentsReg, PtrContentsReg);
   }
 
   if (DestTy == IceType_i64) {
-    Context.insert(InstFakeUse::create(Func, PtrContentsReg));
+    Context.insert<InstFakeUse>(PtrContentsReg);
   }
   lowerAssign(InstAssign::create(Func, Dest, PtrContentsReg));
   if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
-    Context.insert(InstFakeUse::create(Func, Dest64->getLo()));
-    Context.insert(InstFakeUse::create(Func, Dest64->getHi()));
+    Context.insert<InstFakeUse>(Dest64->getLo());
+    Context.insert<InstFakeUse>(Dest64->getHi());
   } else {
-    Context.insert(InstFakeUse::create(Func, Dest));
+    Context.insert<InstFakeUse>(Dest);
   }
 }
 
 void TargetARM32::postambleCtpop64(const InstCall *Instr) {
   Operand *Arg0 = Instr->getArg(0);
   if (isInt32Asserting32Or64(Arg0->getType())) {
     return;
   }
   // The popcount helpers always return 32-bit values, while the intrinsic's
   // signature matches some 64-bit platform's native instructions and expect to
@@ skipping 57 matching lines @@
       _ldrex(T, formMemoryOperand(Instr->getArg(0), IceType_i64));
     } else {
       T = makeReg(DestTy);
       _ldr(T, formMemoryOperand(Instr->getArg(0), DestTy));
     }
     _dmb();
     lowerAssign(InstAssign::create(Func, Dest, T));
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
     // Since lowerLoad may fuse the load w/ an arithmetic instruction, insert
     // the FakeUse on the last-inserted instruction's dest.
-    Context.insert(
-        InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
+    Context.insert<InstFakeUse>(Context.getLastInserted()->getDest());
     return;
   }
   case Intrinsics::AtomicStore: {
     // We require the memory address to be naturally aligned. Given that is the
     // case, then normal loads are atomic.
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(2)))) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }
@@ skipping 25 matching lines @@
       auto *Retry = InstARM32Label::create(Func, this);
       Variable64On32 *NewReg = makeI64RegPair();
       ValueVar->initHiLo(Func);
       ValueVar->mustNotHaveReg();
 
       _dmb();
       lowerAssign(InstAssign::create(Func, ValueVar, Value));
       lowerAssign(InstAssign::create(Func, AddrVar, Addr));
 
       Context.insert(Retry);
-      Context.insert(InstFakeDef::create(Func, NewReg));
+      Context.insert<InstFakeDef>(NewReg);
       lowerAssign(InstAssign::create(Func, NewReg, ValueVar));
       Mem = formMemoryOperand(AddrVar, IceType_i64);
       _ldrex(Tmp, Mem);
       // This fake-use both prevents the ldrex from being dead-code eliminated,
       // while also keeping liveness happy about all defs being used.
-      Context.insert(
-          InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
+      Context.insert<InstFakeUse>(Context.getLastInserted()->getDest());
       _strex(Success, NewReg, Mem);
       _cmp(Success, _0);
       _br(Retry, CondARM32::NE);
 
-      Context.insert(InstFakeUse::create(Func, ValueVar->getLo()));
-      Context.insert(InstFakeUse::create(Func, ValueVar->getHi()));
-      Context.insert(InstFakeUse::create(Func, AddrVar));
+      Context.insert<InstFakeUse>(ValueVar->getLo());
+      Context.insert<InstFakeUse>(ValueVar->getHi());
+      Context.insert<InstFakeUse>(AddrVar);
       _dmb();
       return;
     }
     // non-64-bit stores are atomically as long as the address is aligned. This
     // is PNaCl, so addresses are aligned.
     Variable *T = makeReg(ValueTy);
 
     _dmb();
     lowerAssign(InstAssign::create(Func, T, Value));
     _str(T, formMemoryOperand(Addr, ValueTy));
@@ skipping 77 matching lines @@
     } else {
       TmpReg = makeReg(DestTy);
       New = Func->makeVariable(DestTy);
       NewReg = makeReg(DestTy);
       Expected = Func->makeVariable(DestTy);
       ExpectedReg = makeReg(DestTy);
     }
 
     Mem = formMemoryOperand(Instr->getArg(0), DestTy);
     if (DestTy == IceType_i64) {
-      Context.insert(InstFakeDef::create(Func, Expected));
+      Context.insert<InstFakeDef>(Expected);
     }
     lowerAssign(InstAssign::create(Func, Expected, Instr->getArg(1)));
     if (DestTy == IceType_i64) {
-      Context.insert(InstFakeDef::create(Func, New));
+      Context.insert<InstFakeDef>(New);
     }
     lowerAssign(InstAssign::create(Func, New, Instr->getArg(2)));
     _dmb();
 
     Context.insert(Retry);
     if (DestTy == IceType_i64) {
-      Context.insert(InstFakeDef::create(Func, ExpectedReg, Expected));
+      Context.insert<InstFakeDef>(ExpectedReg, Expected);
     }
     lowerAssign(InstAssign::create(Func, ExpectedReg, Expected));
     if (DestTy == IceType_i64) {
-      Context.insert(InstFakeDef::create(Func, NewReg, New));
+      Context.insert<InstFakeDef>(NewReg, New);
     }
     lowerAssign(InstAssign::create(Func, NewReg, New));
 
     _ldrex(TmpReg, Mem);
-    Context.insert(
-        InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
+    Context.insert<InstFakeUse>(Context.getLastInserted()->getDest());
     if (DestTy == IceType_i64) {
       auto *TmpReg64 = llvm::cast<Variable64On32>(TmpReg);
       auto *ExpectedReg64 = llvm::cast<Variable64On32>(ExpectedReg);
       // lowerAssign above has added fake-defs for TmpReg and ExpectedReg. Let's
       // keep liveness happy, shall we?
-      Context.insert(InstFakeUse::create(Func, TmpReg));
-      Context.insert(InstFakeUse::create(Func, ExpectedReg));
+      Context.insert<InstFakeUse>(TmpReg);
+      Context.insert<InstFakeUse>(ExpectedReg);
       _cmp(TmpReg64->getHi(), ExpectedReg64->getHi());
       _cmp(TmpReg64->getLo(), ExpectedReg64->getLo(), CondARM32::EQ);
     } else {
       _cmp(TmpReg, ExpectedReg);
     }
     _strex(Success, NewReg, Mem, CondARM32::EQ);
     if (DestTy == IceType_i64) {
       auto *TmpReg64 = llvm::cast<Variable64On32>(TmpReg);
       auto *Expected64 = llvm::cast<Variable64On32>(Expected);
       _mov_redefined(Expected64->getHi(), TmpReg64->getHi(), CondARM32::NE);
       _mov_redefined(Expected64->getLo(), TmpReg64->getLo(), CondARM32::NE);
-      auto *FakeDef = InstFakeDef::create(Func, Expected, TmpReg);
-      Context.insert(FakeDef);
-      FakeDef->setDestRedefined();
+      Context.insert<InstFakeDef>(Expected, TmpReg);
+      _set_dest_redefined();
     } else {
       _mov_redefined(Expected, TmpReg, CondARM32::NE);
     }
     _cmp(Success, _0, CondARM32::EQ);
     _br(Retry, CondARM32::NE);
     _dmb();
     lowerAssign(InstAssign::create(Func, Dest, Expected));
-    Context.insert(InstFakeUse::create(Func, Expected));
+    Context.insert<InstFakeUse>(Expected);
     if (auto *New64 = llvm::dyn_cast<Variable64On32>(New)) {
-      Context.insert(InstFakeUse::create(Func, New64->getLo()));
-      Context.insert(InstFakeUse::create(Func, New64->getHi()));
+      Context.insert<InstFakeUse>(New64->getLo());
+      Context.insert<InstFakeUse>(New64->getHi());
     } else {
-      Context.insert(InstFakeUse::create(Func, New));
+      Context.insert<InstFakeUse>(New);
     }
     return;
   }
   case Intrinsics::AtomicRMW: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)))) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
     lowerAtomicRMW(
@@ skipping 71 matching lines @@
       ValLoR = T;
     }
     lowerCLZ(Dest, ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Fabs: {
     Type DestTy = Dest->getType();
     Variable *T = makeReg(DestTy);
     if (isVectorType(DestTy)) {
       // Add a fake def to keep liveness consistent in the meantime.
-      Context.insert(InstFakeDef::create(Func, T));
+      Context.insert<InstFakeDef>(T);
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
       return;
     }
     _vabs(T, legalizeToReg(Instr->getArg(0)));
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Longjmp: {
     llvm::report_fatal_error("longjmp should have been prelowered.");
@@ skipping 444 matching lines @@
     // [OffsetReg{, LSL Shamt}{, #OffsetImm}] is not legal in ARM, so we have to
     // legalize the addressing mode to [BaseReg, OffsetReg{, LSL Shamt}].
     // Instead of a zeroed BaseReg, we initialize it with OffsetImm:
     //
     // [OffsetReg{, LSL Shamt}{, #OffsetImm}] ->
     //     mov BaseReg, #OffsetImm
     //     use of [BaseReg, OffsetReg{, LSL Shamt}]
     //
     const Type PointerType = getPointerType();
     BaseVar = makeReg(PointerType);
-    Context.insert(
-        InstAssign::create(Func, BaseVar, Ctx->getConstantInt32(OffsetImm)));
+    Context.insert<InstAssign>(BaseVar, Ctx->getConstantInt32(OffsetImm));
     OffsetImm = 0;
   } else if (OffsetImm != 0) {
     // ARM Ldr/Str instructions have limited range immediates. The formation
     // loop above materialized an Immediate carelessly, so we ensure the
     // generated offset is sane.
     const int32_t PositiveOffset = OffsetImm > 0 ? OffsetImm : -OffsetImm;
     const InstArithmetic::OpKind Op =
         OffsetImm > 0 ? InstArithmetic::Add : InstArithmetic::Sub;
 
     if (!CanHaveImm || !isLegalMemOffset(Ty, OffsetImm) ||
@@ skipping 10 matching lines @@
         // here and don't form any address mode.
         return nullptr;
       }
       // We formed [Base, Offset {, LSL Amnt}, #const]. Oops. Legalize it to
       //
       // [Base, Offset, {LSL amount}, #const] ->
       //      add T, Base, #const
       //      use of [T, Offset {, LSL amount}]
       const Type PointerType = getPointerType();
       Variable *T = makeReg(PointerType);
-      Context.insert(InstArithmetic::create(
-          Func, Op, T, BaseVar, Ctx->getConstantInt32(PositiveOffset)));
+      Context.insert<InstArithmetic>(Op, T, BaseVar,
+                                     Ctx->getConstantInt32(PositiveOffset));
       BaseVar = T;
       OffsetImm = 0;
     }
   }
 
   assert(BaseVar != nullptr);
   assert(OffsetImm == 0 || OffsetReg == nullptr);
   assert(OffsetReg == nullptr || CanHaveIndex);
   assert(OffsetImm < 0 ? (ValidImmMask & -OffsetImm) == -OffsetImm
                        : (ValidImmMask & OffsetImm) == OffsetImm);
 
   if (OffsetReg != nullptr) {
     Variable *OffsetR = makeReg(getPointerType());
-    Context.insert(InstAssign::create(Func, OffsetR, OffsetReg));
+    Context.insert<InstAssign>(OffsetR, OffsetReg);
     return OperandARM32Mem::create(Func, Ty, BaseVar, OffsetR, ShiftKind,
                                    OffsetRegShamt);
   }
 
   return OperandARM32Mem::create(
       Func, Ty, BaseVar,
       llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(OffsetImm)));
 }
 
 void TargetARM32::doAddressOptLoad() {
   Inst *Instr = Context.getCur();
   assert(llvm::isa<InstLoad>(Instr));
   Variable *Dest = Instr->getDest();
   Operand *Addr = Instr->getSrc(0);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Dest->getType(), Func, Instr, Addr)) {
     Instr->setDeleted();
-    Context.insert(InstLoad::create(Func, Dest, Mem));
+    Context.insert<InstLoad>(Dest, Mem);
   }
 }
 
 void TargetARM32::randomlyInsertNop(float Probability,
                                     RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     UnimplementedError(Func->getContext()->getFlags());
   }
 }
 
 void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetARM32::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = Inst->getRetValue();
     Type Ty = Src0->getType();
     if (Ty == IceType_i64) {
       Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
       Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
-      Context.insert(InstFakeUse::create(Func, R1));
+      Context.insert<InstFakeUse>(R1);
     } else if (Ty == IceType_f32) {
       Variable *S0 = legalizeToReg(Src0, RegARM32::Reg_s0);
       Reg = S0;
     } else if (Ty == IceType_f64) {
       Variable *D0 = legalizeToReg(Src0, RegARM32::Reg_d0);
       Reg = D0;
     } else if (isVectorType(Src0->getType())) {
       Variable *Q0 = legalizeToReg(Src0, RegARM32::Reg_q0);
       Reg = Q0;
     } else {
       Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex);
       Reg = makeReg(Src0F->getType(), RegARM32::Reg_r0);
       _mov(Reg, Src0F, CondARM32::AL);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because addEpilog
   // explicitly looks for a ret instruction as a marker for where to insert the
   // frame removal instructions. addEpilog is responsible for restoring the
   // "lr" register as needed prior to this ret instruction.
   _ret(getPhysicalRegister(RegARM32::Reg_lr), Reg);
 
   // Add a fake use of sp to make sure sp stays alive for the entire function.
   // Otherwise post-call sp adjustments get dead-code eliminated.
   // TODO: Are there more places where the fake use should be inserted? E.g.
   // "void f(int n){while(1) g(n);}" may not have a ret instruction.
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
-  Context.insert(InstFakeUse::create(Func, SP));
+  Context.insert<InstFakeUse>(SP);
 }
 
 void TargetARM32::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(DestTy)) {
     Variable *T = makeReg(DestTy);
-    Context.insert(InstFakeDef::create(Func, T));
+    Context.insert<InstFakeDef>(T);
     _mov(Dest, T);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 
   lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF));
 }
 
 void TargetARM32::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
@@ skipping 14 matching lines @@
 }
 
 void TargetARM32::doAddressOptStore() {
   Inst *Instr = Context.getCur();
   assert(llvm::isa<InstStore>(Instr));
   Operand *Src = Instr->getSrc(0);
   Operand *Addr = Instr->getSrc(1);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Src->getType(), Func, Instr, Addr)) {
     Instr->setDeleted();
-    Context.insert(InstStore::create(Func, Src, Mem));
+    Context.insert<InstStore>(Src, Mem);
   }
 }
 
 void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
@@ skipping 37 matching lines @@
 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) {
   _trap();
 }
 
 void TargetARM32::prelowerPhis() {
   PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func);
 }
 
 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
-  Context.insert(InstFakeDef::create(Func, Reg));
+  Context.insert<InstFakeDef>(Reg);
   UnimplementedError(Func->getContext()->getFlags());
   return Reg;
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Src)) {
@@ skipping 153 matching lines @@
         Variable *T = makeReg(Ty, RegNum);
         _mov(T,
              OperandARM32FlexFpImm::create(Func, From->getType(), ModifiedImm));
         return T;
       }
 
       if (Ty == IceType_f64 && isFloatingPointZero(From)) {
         // Use T = T ^ T to load a 64-bit fp zero. This does not work for f32
         // because ARM does not have a veor instruction with S registers.
         Variable *T = makeReg(IceType_f64, RegNum);
-        Context.insert(InstFakeDef::create(Func, T));
+        Context.insert<InstFakeDef>(T);
         _veor(T, T, T);
         return T;
       }
 
       // Load floats/doubles from literal pool.
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
       llvm::cast<Constant>(From)->emitPoolLabel(StrBuf, Ctx);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
@@ skipping 607 matching lines @@
 }
 
 InstARM32Call *TargetARM32::Sandboxer::bl(Variable *ReturnReg,
                                           Operand *CallTarget) {
   if (Target->NeedSandboxing) {
     if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
       Target->_bic(CallTargetR, CallTargetR,
                    indirectBranchBicMask(Target->Func));
     }
   }
-  auto *Call = InstARM32Call::create(Target->Func, ReturnReg, CallTarget);
-  Target->Context.insert(Call);
-  return Call;
+  return Target->Context.insert<InstARM32Call>(ReturnReg, CallTarget);
 }
 
 void TargetARM32::Sandboxer::ldr(Variable *Dest, OperandARM32Mem *Mem,
                                  CondARM32::Cond Pred) {
   Variable *MemBase = Mem->getBase();
   if (Target->NeedSandboxing && baseNeedsBic(MemBase)) {
     assert(!Mem->isRegReg());
     Target->_bic(MemBase, MemBase, memOpBicMask(Target->Func), Pred);
   }
   Target->_ldr(Dest, Mem, Pred);
@@ skipping 240 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice