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1 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===// | 1 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 /// \file | 10 /// \file |
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132 | 132 |
133 void InstMIPS32Ret::emit(const Cfg *Func) const { | 133 void InstMIPS32Ret::emit(const Cfg *Func) const { |
134 if (!BuildDefs::dump()) | 134 if (!BuildDefs::dump()) |
135 return; | 135 return; |
136 assert(getSrcSize() > 0); | 136 assert(getSrcSize() > 0); |
137 auto *RA = llvm::cast<Variable>(getSrc(0)); | 137 auto *RA = llvm::cast<Variable>(getSrc(0)); |
138 assert(RA->hasReg()); | 138 assert(RA->hasReg()); |
139 assert(RA->getRegNum() == RegMIPS32::Reg_RA); | 139 assert(RA->getRegNum() == RegMIPS32::Reg_RA); |
140 Ostream &Str = Func->getContext()->getStrEmit(); | 140 Ostream &Str = Func->getContext()->getStrEmit(); |
141 Str << "\t" | 141 Str << "\t" |
142 << "jr" | 142 "jr" |
143 << "\t"; | 143 "\t"; |
144 RA->emit(Func); | 144 RA->emit(Func); |
145 } | 145 } |
146 | 146 |
147 void InstMIPS32Ret::emitIAS(const Cfg *Func) const { | 147 void InstMIPS32Ret::emitIAS(const Cfg *Func) const { |
148 (void)Func; | 148 (void)Func; |
149 llvm_unreachable("Not yet implemented"); | 149 llvm_unreachable("Not yet implemented"); |
150 } | 150 } |
151 | 151 |
152 void InstMIPS32Ret::dump(const Cfg *Func) const { | 152 void InstMIPS32Ret::dump(const Cfg *Func) const { |
153 if (!BuildDefs::dump()) | 153 if (!BuildDefs::dump()) |
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251 Operand *Src = getSrc(0); | 251 Operand *Src = getSrc(0); |
252 auto *S = llvm::dyn_cast<Variable>(Src); | 252 auto *S = llvm::dyn_cast<Variable>(Src); |
253 Str << "\t"; | 253 Str << "\t"; |
254 if (Dest->hasReg()) { | 254 if (Dest->hasReg()) { |
255 if (S && S->hasReg()) | 255 if (S && S->hasReg()) |
256 Str << "move"; | 256 Str << "move"; |
257 else | 257 else |
258 Str << "lw"; | 258 Str << "lw"; |
259 } else { | 259 } else { |
260 if (S && S->hasReg()) { | 260 if (S && S->hasReg()) { |
261 Str << "sw"; | 261 Str << "sw" |
262 Str << "\t"; | 262 "\t"; |
263 getSrc(0)->emit(Func); | 263 getSrc(0)->emit(Func); |
264 Str << ", "; | 264 Str << ", "; |
265 getDest()->emit(Func); | 265 getDest()->emit(Func); |
266 return; | 266 return; |
267 } else | 267 } else |
268 Str << "move"; | 268 Str << "move"; |
269 } | 269 } |
270 | 270 |
271 Str << "\t"; | 271 Str << "\t"; |
272 getDest()->emit(Func); | 272 getDest()->emit(Func); |
273 Str << ", "; | 273 Str << ", "; |
274 getSrc(0)->emit(Func); | 274 getSrc(0)->emit(Func); |
275 } | 275 } |
276 | 276 |
277 } // end of namespace Ice | 277 } // end of namespace Ice |
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