Add CLZ instruction to the ARM integrated assembler.

tests_lit/assembler/arm32/clz.ll

Index: tests_lit/assembler/arm32/clz.ll
diff --git a/tests_lit/assembler/arm32/clz.ll b/tests_lit/assembler/arm32/clz.ll
new file mode 100644
index 0000000000000000000000000000000000000000..5bd4a7818a93260a143922f4682029ec54ca56ae
--- /dev/null
+++ b/tests_lit/assembler/arm32/clz.ll
@@ -0,0 +1,66 @@
+; Show that we know how to translate clz.
+
+; NOTE: We use -Om1 to get rid of memory stores.

[Jim Stichnoth, 2015/12/11 23:44:34]

All the other .ll files with this comment say the -O2 is used to get rid of
memory stores.  What's the real reason for -Om1 here?

I assume that as a general principle, Om1 is used to maximize stability of test
output, so maybe this comment just gets deleted?

[Karl, 2015/12/17 16:02:40]

Yes, I wanted to maximize stability in this case. Removing comment.

+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define internal i32 @testClz(i32 %a) {
+; ASM-LABEL:testClz:
+; DIS-LABEL:00000000 <testClz>:
+; IASM-LABEL:testClz:
+
+entry:
+; ASM-NEXT:.LtestClz$entry:
+; IASM-NEXT:.LtestClz$entry:
+
+; ASM-NEXT:     sub     sp, sp, #8
+; DIS-NEXT:   0:        e24dd008
+; IASM-NEXT:	.byte 0x8
+; IASM-NEXT:	.byte 0xd0
+; IASM-NEXT:	.byte 0x4d
+; IASM-NEXT:	.byte 0xe2
+
+; ASM-NEXT:     str     r0, [sp, #4]
+; ASM-NEXT:     # [sp, #4] = def.pseudo 
+; DIS-NEXT:   4:        e58d0004
+; IASM-NEXT:	.byte 0x4
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x8d
+; IASM-NEXT:	.byte 0xe5
+
+  %x = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
+
+; ASM-NEXT:     ldr     r0, [sp, #4]
+; DIS-NEXT:   8:        e59d0004
+; IASM-NEXT:	.byte 0x4
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x9d
+; IASM-NEXT:	.byte 0xe5
+
+; ASM-NEXT:     clz     r0, r0
+; DIS-NEXT:   c:        e16f0f10
+; IASM-NEXT:	.byte 0x10
+; IASM-NEXT:	.byte 0xf
+; IASM-NEXT:	.byte 0x6f
+; IASM-NEXT:	.byte 0xe1
+
+  ret i32 %x
+}