Add CLZ instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1069 matching lines @@
   constexpr const char *BxName = "bx";
   verifyCondDefined(Cond, BxName);
   verifyRegDefined(Rm, "Rm", BxName);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                            B21 | (0xfff << 8) | B4 |
                            (encodeGPRRegister(Rm) << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::clz(const Operand *OpRd, const Operand *OpSrc,
+                         CondARM32::Cond Cond) {
+  // CLZ - ARM section A8.8.33, encoding A1:
+  //   clz<c> <Rd> <Rm>
+  //
+  // cccc000101101111dddd11110001mmmm where cccc=Cond, dddd=Rd, and mmmm=Rm.
+  constexpr const char *ClzName = "clz";
+  constexpr const char *RdName = "Rd";
+  constexpr const char *RmName = "Rm";
+  IValueT Rd = encodeRegister(OpRd, RdName, ClzName);
+  verifyRegDefined(Rd, RdName, ClzName);
+  verifyRegNotPc(Rd, RdName, ClzName);
+  IValueT Rm = encodeRegister(OpSrc, RmName, ClzName);
+  verifyRegDefined(Rm, RmName, ClzName);
+  verifyRegNotPc(Rm, RmName, ClzName);
+  verifyCondDefined(Cond, ClzName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr IValueT PredefinedBits =
+      B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4;
+  const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) |
+                           (Rd << kRdShift) | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::cmn(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // CMN (immediate) - ARM section A8.8.34, encoding A1:
   //   cmn<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110111nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   //
   // CMN (register) - ARM section A8.8.35, encodeing A1:
   //   cmn<c> <Rn>, <Rm>{, <shift>}
@@ skipping 678 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice