Add trap (an UDF instruction) to the ARM integrated Assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 96 matching lines @@
     }
   }
 
   MoveRelocatableFixup *createMoveFixup(bool IsMovW, const Constant *Value);
 
   BlRelocatableFixup *createBlFixup(const ConstantRelocatable *BlTarget);
 
   void alignFunction() override {
     const SizeT Align = 1 << getBundleAlignLog2Bytes();
     SizeT BytesNeeded = Utils::OffsetToAlignment(Buffer.getPosition(), Align);
-    constexpr IValueT UndefinedInst = 0xe7fedef0; // udf #60896
     constexpr SizeT InstSize = sizeof(IValueT);
     assert(BytesNeeded % InstARM32::InstSize == 0);
     while (BytesNeeded > 0) {
-      AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-      emitInst(UndefinedInst);
+      trap();
       BytesNeeded -= InstSize;
     }
   }
 
   SizeT getBundleAlignLog2Bytes() const override { return 4; }
 
   const char *getAlignDirective() const override { return ".p2alignl"; }
 
-  llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override {
-    // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0
-    // http://llvm.org/viewvc/llvm-project?view=revision&revision=173943
-    static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0};
-    return llvm::ArrayRef<uint8_t>(Padding, 4);
-  }
+  llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override;
 
   void padWithNop(intptr_t Padding) override;
 
   Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override {
     assert(NodeNumber < CfgNodeLabels.size());
     return CfgNodeLabels[NodeNumber];
   }
 
   Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
     return getOrCreateLabel(NodeNumber, CfgNodeLabels);
@@ skipping 153 matching lines @@
     const TargetInfo TInfo(Lowering);
     strex(OpRd, OpRt, OpAddress, Cond, TInfo);
   }
 
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   // Implements sxtb/sxth depending on type of OpSrc0.
   void sxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
+  void trap();
+
   void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
@@ skipping 131 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H