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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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1709 // sub{s}<c> sp, <Rn>, #<RotatedImm8> | 1709 // sub{s}<c> sp, <Rn>, #<RotatedImm8> |
1710 // | 1710 // |
1711 // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn, | 1711 // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn, |
1712 // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8 | 1712 // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8 |
1713 constexpr const char *SubName = "sub"; | 1713 constexpr const char *SubName = "sub"; |
1714 constexpr IValueT SubOpcode = B1; // 0010 | 1714 constexpr IValueT SubOpcode = B1; // 0010 |
1715 emitType01(Cond, SubOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, | 1715 emitType01(Cond, SubOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, |
1716 SubName); | 1716 SubName); |
1717 } | 1717 } |
1718 | 1718 |
1719 // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0 | |
1720 // http://llvm.org/viewvc/llvm-project?view=revision&revision=173943 | |
1721 const uint8_t AssemblerARM32::TrapInst[4] = {0xE7, 0xFE, 0xDE, 0xF0}; | |
Jim Stichnoth
2015/12/11 23:31:08
I think you can omit the "4".
Karl
2015/12/17 16:23:09
Done.
| |
1722 | |
1723 void AssemblerARM32::trap() { | |
1724 AssemblerBuffer::EnsureCapacity ensured(&Buffer); | |
1725 for (size_t i = 1, len = llvm::array_lengthof(TrapInst); i <= len; ++i) | |
Jim Stichnoth
2015/12/11 23:31:08
Hmm, I would use a "more familiar" form of the loo
Karl
2015/12/17 16:23:09
Done.
| |
1726 Buffer.emit<uint8_t>(TrapInst[len - i]); | |
1727 } | |
1728 | |
1719 void AssemblerARM32::tst(const Operand *OpRn, const Operand *OpSrc1, | 1729 void AssemblerARM32::tst(const Operand *OpRn, const Operand *OpSrc1, |
1720 CondARM32::Cond Cond) { | 1730 CondARM32::Cond Cond) { |
1721 // TST (register) - ARM section A8.8.241, encoding A1: | 1731 // TST (register) - ARM section A8.8.241, encoding A1: |
1722 // tst<c> <Rn>, <Rm>(, <shift>} | 1732 // tst<c> <Rn>, <Rm>(, <shift>} |
1723 // | 1733 // |
1724 // cccc00010001nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, | 1734 // cccc00010001nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, |
1725 // iiiii=Shift, and tt=ShiftKind. | 1735 // iiiii=Shift, and tt=ShiftKind. |
1726 // | 1736 // |
1727 // TST (immediate) - ARM section A8.8.240, encoding A1: | 1737 // TST (immediate) - ARM section A8.8.240, encoding A1: |
1728 // tst<c> <Rn>, #<RotatedImm8> | 1738 // tst<c> <Rn>, #<RotatedImm8> |
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1778 | 1788 |
1779 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, | 1789 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, |
1780 CondARM32::Cond Cond) { | 1790 CondARM32::Cond Cond) { |
1781 constexpr const char *UxtName = "uxt"; | 1791 constexpr const char *UxtName = "uxt"; |
1782 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; | 1792 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; |
1783 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); | 1793 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); |
1784 } | 1794 } |
1785 | 1795 |
1786 } // end of namespace ARM32 | 1796 } // end of namespace ARM32 |
1787 } // end of namespace Ice | 1797 } // end of namespace Ice |
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