Index: src/IceAssemblerARM32.cpp |
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp |
index 2ef7e2f8a0174071af5b8e2c86007761c2e86eb5..9dba4c994e9021cd2b30fb2ebe9bbec00f885b85 100644 |
--- a/src/IceAssemblerARM32.cpp |
+++ b/src/IceAssemblerARM32.cpp |
@@ -41,6 +41,10 @@ static constexpr IValueT B4 = 1 << 4; |
static constexpr IValueT B5 = 1 << 5; |
static constexpr IValueT B6 = 1 << 6; |
static constexpr IValueT B7 = 1 << 7; |
+static constexpr IValueT B8 = 1 << 8; |
+static constexpr IValueT B9 = 1 << 9; |
+static constexpr IValueT B10 = 1 << 10; |
+static constexpr IValueT B11 = 1 << 11; |
static constexpr IValueT B12 = 1 << 12; |
static constexpr IValueT B13 = 1 << 13; |
static constexpr IValueT B14 = 1 << 14; |
@@ -1591,6 +1595,23 @@ void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn, |
MulName); |
} |
+void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpSrc, |
+ CondARM32::Cond Cond) { |
+ // REV - ARM section A8.8.145, encoding A1: |
+ // rev <Rd>, <Rm> |
+ // |
+ // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm. |
+ constexpr const char *RevName = "rev"; |
+ IValueT Rd = encodeRegister(OpRd, "Rd", RevName); |
+ IValueT Rm = encodeRegister(OpSrc, "Rm", RevName); |
+ AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
+ constexpr IValueT Opcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | |
+ B16 | B11 | B10 | B9 | B8 | B5 | B4; |
+ IValueT Encoding = |
+ (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift); |
+ emitInst(Encoding); |
+} |
+ |
void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn, |
const Operand *OpSrc1, bool SetFlags, |
CondARM32::Cond Cond) { |