Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(182)

Side by Side Diff: src/IceAssemblerARM32.h

Issue 1517863002: Add translation of REV in ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « no previous file | src/IceAssemblerARM32.cpp » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 240 matching lines...) Expand 10 before | Expand all | Expand 10 after
251 void pop(const Operand *OpRt, CondARM32::Cond Cond); 251 void pop(const Operand *OpRt, CondARM32::Cond Cond);
252 252
253 // Note: Registers is a bitset, where bit n corresponds to register Rn. 253 // Note: Registers is a bitset, where bit n corresponds to register Rn.
254 void popList(const IValueT Registers, CondARM32::Cond Cond); 254 void popList(const IValueT Registers, CondARM32::Cond Cond);
255 255
256 void push(const Operand *OpRt, CondARM32::Cond Cond); 256 void push(const Operand *OpRt, CondARM32::Cond Cond);
257 257
258 // Note: Registers is a bitset, where bit n corresponds to register Rn. 258 // Note: Registers is a bitset, where bit n corresponds to register Rn.
259 void pushList(const IValueT Registers, CondARM32::Cond Cond); 259 void pushList(const IValueT Registers, CondARM32::Cond Cond);
260 260
261 void rev(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
262
261 void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 263 void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
262 bool SetFlags, CondARM32::Cond Cond); 264 bool SetFlags, CondARM32::Cond Cond);
263 265
264 void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 266 void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
265 bool SetFlags, CondARM32::Cond Cond); 267 bool SetFlags, CondARM32::Cond Cond);
266 268
267 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 269 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
268 bool SetFlags, CondARM32::Cond Cond); 270 bool SetFlags, CondARM32::Cond Cond);
269 271
270 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 272 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
(...skipping 152 matching lines...) Expand 10 before | Expand all | Expand 10 after
423 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and 425 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
424 // iiiiiiiiiiiiiiii=Imm16. 426 // iiiiiiiiiiiiiiii=Imm16.
425 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, 427 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
426 const Operand *OpSrc, const char *MovName); 428 const Operand *OpSrc, const char *MovName);
427 }; 429 };
428 430
429 } // end of namespace ARM32 431 } // end of namespace ARM32
430 } // end of namespace Ice 432 } // end of namespace Ice
431 433
432 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 434 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
OLDNEW
« no previous file with comments | « no previous file | src/IceAssemblerARM32.cpp » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698