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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1517863002: Add translation of REV in ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Reformat source. Created 5 years ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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251 void pop(const Operand *OpRt, CondARM32::Cond Cond); 251 void pop(const Operand *OpRt, CondARM32::Cond Cond);
252 252
253 // Note: Registers is a bitset, where bit n corresponds to register Rn. 253 // Note: Registers is a bitset, where bit n corresponds to register Rn.
254 void popList(const IValueT Registers, CondARM32::Cond Cond); 254 void popList(const IValueT Registers, CondARM32::Cond Cond);
255 255
256 void push(const Operand *OpRt, CondARM32::Cond Cond); 256 void push(const Operand *OpRt, CondARM32::Cond Cond);
257 257
258 // Note: Registers is a bitset, where bit n corresponds to register Rn. 258 // Note: Registers is a bitset, where bit n corresponds to register Rn.
259 void pushList(const IValueT Registers, CondARM32::Cond Cond); 259 void pushList(const IValueT Registers, CondARM32::Cond Cond);
260 260
261 void rev(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
262
261 void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 263 void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
262 bool SetFlags, CondARM32::Cond Cond); 264 bool SetFlags, CondARM32::Cond Cond);
263 265
264 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 266 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
265 bool SetFlags, CondARM32::Cond Cond); 267 bool SetFlags, CondARM32::Cond Cond);
266 268
267 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 269 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
268 CondARM32::Cond Cond); 270 CondARM32::Cond Cond);
269 271
270 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 272 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
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420 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and 422 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
421 // iiiiiiiiiiiiiiii=Imm16. 423 // iiiiiiiiiiiiiiii=Imm16.
422 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, 424 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
423 const Operand *OpSrc, const char *MovName); 425 const Operand *OpSrc, const char *MovName);
424 }; 426 };
425 427
426 } // end of namespace ARM32 428 } // end of namespace ARM32
427 } // end of namespace Ice 429 } // end of namespace Ice
428 430
429 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 431 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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