Add various forms of LDREX/STREX to ARM integrated assembler.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 0dbff60651726a193515416843a116c8acc6a353..54f51c1b82f64f8b2dea9ba96201dcdba4205061 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -223,6 +223,15 @@ public:
     ldr(OpRt, OpAddress, Cond, TInfo);
   }
 
+  void ldrex(const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void ldrex(const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    ldrex(OpRt, OpAddress, Cond, TInfo);
+  }
+
   void lsl(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
@@ -281,6 +290,15 @@ public:
     str(OpRt, OpAddress, Cond, TInfo);
   }
 
+  void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    strex(OpRd, OpRt, OpAddress, Cond, TInfo);
+  }
+
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
@@ -376,6 +394,12 @@ private:
                      const Operand *OpAddress, const TargetInfo &TInfo,
                      const char *InstName);
 
+  // Emit cccc00011xxlnnnndddd11111001tttt where cccc=Cond, xx encodes type
+  // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt.
+  void emitMemExOp(CondARM32::Cond, Type Ty, bool IsLoad, const Operand *OpRd,
+                   IValueT Rt, const Operand *OpAddress,
+                   const TargetInfo &TInfo, const char *InstName);
+
   // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
   // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
   // rrrrrrrrrrrrrrrr is bitset of Registers.