Add various forms of LDREX/STREX to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 82 matching lines @@
 // Shift instruction register fields encodings.
 static constexpr IValueT kShiftImmShift = 7;
 static constexpr IValueT kShiftImmBits = 5;
 static constexpr IValueT kShiftShift = 5;
 static constexpr IValueT kImmed12Bits = 12;
 static constexpr IValueT kImm12Shift = 0;
 
 // Rotation instructions (uxtb etc.).
 static constexpr IValueT kRotationShift = 10;
 
+// MemEx instructions.
+static constexpr IValueT kMemExOpcodeShift = 20;
+
 // Div instruction register field encodings.
 static constexpr IValueT kDivRdShift = 16;
 static constexpr IValueT kDivRmShift = 8;
 static constexpr IValueT kDivRnShift = 0;
 
 // Type of instruction encoding (bits 25-27). See ARM section A5.1
 static constexpr IValueT kInstTypeDataRegister = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataRegShift = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
 static constexpr IValueT kInstTypeMemImmediate = 2;  // i.e. 010
@@ skipping 57 matching lines @@
 }
 
 // Extract out a Bit in Value.
 bool isBitSet(IValueT Bit, IValueT Value) { return (Value & Bit) == Bit; }
 
 // Returns the GPR register at given Shift in Value.
 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
+// Defines alternate layouts of instruction operands, should the (common)
+// default pattern not be used.
+enum OpEncoding {
+  // No alternate layout specified.
+  DefaultOpEncoding,
+  // Alternate encoding 3 for memory operands (like in strb, strh, ldrb, and
+  // ldrh.
+  OpEncoding3,
+  // Alternate encoding for memory operands for ldrex and strex, which only
+  // actually expect a register.
+  OpEncodingMemEx
+};
+
+IValueT getEncodedGPRegNum(const Variable *Var) {
+  int32_t Reg = Var->getRegNum();
+  return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
+                                        : RegARM32::getEncodedGPR(Reg);
+}
+
 // The way an operand is encoded into a sequence of bits in functions
 // encodeOperand and encodeAddress below.
 enum EncodedOperand {
   // Unable to encode, value left undefined.
   CantEncode = 0,
   // Value is register found.
   EncodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   EncodedAsRotatedImm8,
+  // EncodedAsImmRegOffset is a memory operand that can take three forms, based
+  // on OpEncoding:
+  //
+  // ***** DefaultOpEncoding *****
+  //
   // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
-  EncodedAsImmRegOffset,
+  //
+  // ***** OpEncoding3 *****
+  //
   // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
   // if pre-indexed addressing, u=1 if offset positive, and w=1 if writeback to
   // Rn.
-  EncodedAsImmRegOffsetEnc3,
+  //
+  // ***** OpEncodingMemEx *****
+  //
+  // Value=000000000000nnnn0000000000000000 where nnnn=Rn.
+  EncodedAsImmRegOffset,
   // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
   // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
   // writeback to Rn.
   EncodedAsShiftRotateImm5,
   // Value=000000000000000000000iiiii0000000 where iiii defines the Imm5 value
   // to shift.
   EncodedAsShiftImm5,
   // Value=iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
   // kind, and iiiii is the shift amount.
@@ skipping 25 matching lines @@
 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
                              IValueT Rs) {
   return (Rs << kRsShift) | (encodeShift(Shift) << kShiftShift) | B4 |
          (Rm << kRmShift);
 }
 
 EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
-      Value = Var->getRegNum();
+      Value = getEncodedGPRegNum(Var);
       return EncodedAsRegister;
     }
     return CantEncode;
   }
   if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const IValueT Immed8 = FlexImm->getImm();
     const IValueT Rotate = FlexImm->getRotateAmt();
     if (!((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits))))
       return CantEncode;
     Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
@@ skipping 55 matching lines @@
   IValueT Value = Mode | (Rn << kRnShift);
   if (Imm8 < 0) {
     Imm8 = -Imm8;
     Value = (Value ^ U);
   }
   assert(Imm8 < (1 << 8));
   Value = Value | B22 | ((Imm8 & 0xf0) << 4) | (Imm8 & 0x0f);
   return Value;
 }
 
-// Defines alternate layouts of instruction operands, should the (common)
-// default pattern not be used.
-enum OpEncoding {
-  // No alternate layout specified.
-  DefaultOpEncoding,
-  // Alternate encoding 3.
-  OpEncoding3
-};
+IValueT encodeImmRegOffset(OpEncoding AddressEncoding, IValueT Reg,
+                           IOffsetT Offset, OperandARM32Mem::AddrMode Mode) {
+  switch (AddressEncoding) {
+  case DefaultOpEncoding:
+    return encodeImmRegOffset(Reg, Offset, Mode);
+  case OpEncoding3:
+    return encodeImmRegOffsetEnc3(Reg, Offset, Mode);
+  case OpEncodingMemEx:
+    assert(Offset == 0);
+    assert(Mode == OperandARM32Mem::Offset);
+    return Reg << kRnShift;
+  }
+}
 
 // Encodes memory address Opnd, and encodes that information into Value, based
 // on how ARM represents the address. Returns how the value was encoded.
 EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value,
                              const AssemblerARM32::TargetInfo &TInfo,
                              OpEncoding AddressEncoding = DefaultOpEncoding) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantEncode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantEncode;
     int32_t BaseRegNum = Var->getBaseRegNum();
     if (BaseRegNum == Variable::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
-    Value = encodeImmRegOffset(BaseRegNum, Offset, OperandARM32Mem::Offset);
+    Value = encodeImmRegOffset(AddressEncoding, BaseRegNum, Offset,
+                               OperandARM32Mem::Offset);
     return EncodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantEncode;
-    IValueT Rn = Var->getRegNum();
+    IValueT Rn = getEncodedGPRegNum(Var);
     if (Mem->isRegReg()) {
       const Variable *Index = Mem->getIndex();
       if (Var == nullptr)
         return CantEncode;
       Value = (Rn << kRnShift) | Mem->getAddrMode() |
-              encodeShiftRotateImm5(Index->getRegNum(), Mem->getShiftOp(),
-                                    Mem->getShiftAmt());
+              encodeShiftRotateImm5(getEncodedGPRegNum(Index),
+                                    Mem->getShiftOp(), Mem->getShiftAmt());
       return EncodedAsShiftRotateImm5;
     }
     // Encoded as immediate register offset.
     ConstantInteger32 *Offset = Mem->getOffset();
-    switch (AddressEncoding) {
-    case DefaultOpEncoding:
-      Value = encodeImmRegOffset(Rn, Offset->getValue(), Mem->getAddrMode());
-      return EncodedAsImmRegOffset;
-    case OpEncoding3:
-      Value =
-          encodeImmRegOffsetEnc3(Rn, Offset->getValue(), Mem->getAddrMode());
-      return EncodedAsImmRegOffsetEnc3;
-    }
+    Value = encodeImmRegOffset(AddressEncoding, Rn, Offset->getValue(),
+                               Mem->getAddrMode());
+    return EncodedAsImmRegOffset;
   }
   return CantEncode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
@@ skipping 410 matching lines @@
 
 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode,
                                    IValueT Rt, const Operand *OpAddress,
                                    const TargetInfo &TInfo,
                                    const char *InstName) {
   IValueT Address;
   switch (encodeAddress(OpAddress, Address, TInfo, OpEncoding3)) {
   default:
     llvm::report_fatal_error(std::string(InstName) +
                              ": Memory address not understood");
-  case EncodedAsImmRegOffsetEnc3: {
+  case EncodedAsImmRegOffset: {
     // XXXH (immediate)
     //   xxxh<c> <Rt>, [<Rn>{, #+-<Imm8>}]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu0wxnnnnttttiiiiyyyyjjjj where cccc=Cond, nnnn=Rn, tttt=Rt,
     // iiiijjjj=Imm8, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode,
     // and pu0w0nnnn0000iiii0000jjjj=Address.
     verifyRegDefined(Rt, "Rt", InstName);
     verifyCondDefined(Cond, InstName);
@@ skipping 86 matching lines @@
 }
 
 void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode,
                                     const Operand *OpRd, const Operand *OpSrc0,
                                     const char *InstName) {
   IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
   IValueT Rm = encodeRegister(OpSrc0, "Rm", InstName);
   // Note: For the moment, we assume no rotation is specified.
   RotationValue Rotation = kRotateNone;
   constexpr IValueT Rn = RegARM32::Encoded_Reg_pc;
-  switch (typeWidthInBytes(OpSrc0->getType())) {
+  const Type Ty = OpSrc0->getType();
+  switch (Ty) {
   default:
-    llvm::report_fatal_error(std::string(InstName) +
-                             ": Type of Rm not understood");
+    llvm::report_fatal_error(std::string(InstName) + ": Type " +
+                             typeString(Ty) + " not allowed");
     break;
-  case 1: {
+  case IceType_i1:
+  case IceType_i8: {
     // SXTB/UXTB - Arm sections A8.8.233 and A8.8.274, encoding A1:
     //   sxtb<c> <Rd>, <Rm>{, <rotate>}
     //   uxtb<c> <Rd>, <Rm>{, <rotate>}
     //
     // ccccxxxxxxxx1111ddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
     // dddd=Rd, mmmm=Rm, and rr defined (RotationValue) rotate.
     break;
   }
-  case 2: {
+  case IceType_i16: {
     // SXTH/UXTH - ARM sections A8.8.235 and A8.8.276, encoding A1:
     //   uxth<c> <Rd>< <Rm>{, <rotate>}
     //
     // cccc01101111nnnnddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
     // rr defined (RotationValue) rotate.
     Opcode |= B20;
     break;
   }
   }
 
@@ skipping 222 matching lines @@
   emitType01(Cond, EorOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              EorName);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
   constexpr const char *LdrName = "ldr";
   constexpr bool IsLoad = true;
   IValueT Rt = encodeRegister(OpRt, "Rt", LdrName);
   const Type Ty = OpRt->getType();
-  switch (typeWidthInBytesLog2(Ty)) {
-  case 3:
-  // LDRD is not implemented because target lowering handles i64 and double by
-  // using two (32-bit) load instructions. Note: Intenionally drop to default
-  // case.
+  switch (Ty) {
+  case IceType_i64:
+    // LDRD is not implemented because target lowering handles i64 and double by
+    // using two (32-bit) load instructions. Note: Intentionally drop to default
+    // case.
+    llvm::report_fatal_error(std::string("ldr : Type ") + typeString(Ty) +
+                             " not implemented");
   default:
     llvm::report_fatal_error(std::string("ldr : Type ") + typeString(Ty) +
-                             " not implementable\n");
-  case 0: {
-    // Handles i1 and i8 loads.
-    //
+                             " not allowed");
+  case IceType_i1:
+  case IceType_i8: {
     // LDRB (immediate) - ARM section A8.8.68, encoding A1:
     //   ldrb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
     //   ldrb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
     //   ldrb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
     //
     // cccc010pu1w1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     //
     // LDRB (register) - ARM section A8.8.66, encoding A1:
     //   ldrb<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   ldrb<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
     //
     // cccc011pu1w1nnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt, U=1 if +, pu0b
     // is a BlockAddr, and pu0w0nnnn0000iiiiiss0mmmm=Address.
     constexpr bool IsByte = true;
     emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
     return;
   }
-  case 1: {
-    // Handles i16 loads.
-    //
+  case IceType_i16: {
     // LDRH (immediate) - ARM section A8.8.80, encoding A1:
     //   ldrh<c> <Rt>, [<Rn>{, #+/-<Imm8>}]
     //   ldrh<c> <Rt>, [<Rn>], #+/-<Imm8>
     //   ldrh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu1w1nnnnttttiiii1011iiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiii=Imm8, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     constexpr const char *Ldrh = "ldrh";
     emitMemOpEnc3(Cond, L | B7 | B5 | B4, Rt, OpAddress, TInfo, Ldrh);
     return;
   }
-  case 2: {
-    // Note: Handles i32 and float loads. Target lowering handles i64 and
-    // double by using two (32 bit) load instructions.
-    //
+  case IceType_i32: {
     // LDR (immediate) - ARM section A8.8.63, encoding A1:
     //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
     //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
     //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
     //
     // cccc010pu0w1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +, pu0w is a BlockAddr, and
     //
     // LDR (register) - ARM section A8.8.70, encoding A1:
     //   ldrb<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   ldrb<c> <Rt>, [<Rn>], +-<Rm>{, <shift>}
     //
     // cccc011pu0w1nnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt, U=1 if +, pu0b
     // is a BlockAddr, and pu0w0nnnn0000iiiiiss0mmmm=Address.
     constexpr bool IsByte = false;
     emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
     return;
   }
   }
 }
 
+void AssemblerARM32::emitMemExOp(CondARM32::Cond Cond, Type Ty, bool IsLoad,
+                                 const Operand *OpRd, IValueT Rt,
+                                 const Operand *OpAddress,
+                                 const TargetInfo &TInfo,
+                                 const char *InstName) {
+  IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
+  IValueT MemExOpcode = IsLoad ? B0 : 0;
+  switch (Ty) {
+  default:
+    llvm::report_fatal_error(std::string(InstName) + ": Type " +
+                             typeString(Ty) + " not allowed");
+  case IceType_i1:
+  case IceType_i8:
+    MemExOpcode |= B2;
+    break;
+  case IceType_i16:
+    MemExOpcode |= B2 | B1;
+    break;
+  case IceType_i32:
+    break;
+  case IceType_i64:
+    MemExOpcode |= B1;
+  }
+  IValueT AddressRn;
+  if (encodeAddress(OpAddress, AddressRn, TInfo, OpEncodingMemEx) !=
+      EncodedAsImmRegOffset)
+    llvm::report_fatal_error(std::string(InstName) +
+                             ": Can't extract Rn from address");
+  assert(Utils::IsAbsoluteUint(3, MemExOpcode));
+  verifyRegDefined(Rd, "Rd", InstName);
+  verifyRegDefined(Rt, "Rt", InstName);
+  verifyCondDefined(Cond, InstName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 |
+                     B8 | B7 | B4 | (MemExOpcode << kMemExOpcodeShift) |
+                     AddressRn | (Rd << kRdShift) | (Rt << kRmShift);
+  emitInst(Encoding);
+  return;
+}
+
+void AssemblerARM32::ldrex(const Operand *OpRt, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // LDREXB - ARM section A8.8.76, encoding A1:
+  //   ldrexb<c> <Rt>, [<Rn>]
+  //
+  // cccc00011101nnnntttt111110011111 where cccc=Cond, tttt=Rt, and nnnn=Rn.
+  //
+  // LDREXH - ARM section A8.8.78, encoding A1:
+  //   ldrexh<c> <Rt>, [<Rn>]
+  //
+  // cccc00011111nnnntttt111110011111 where cccc=Cond, tttt=Rt, and nnnn=Rn.
+  //
+  // LDREX - ARM section A8.8.75, encoding A1:
+  //   ldrex<c> <Rt>, [<Rn>]
+  //
+  // cccc00011001nnnntttt111110011111 where cccc=Cond, tttt=Rt, and nnnn=Rn.
+  //
+  // LDREXD - ARM section A8.
+  //   ldrexd<c> <Rt>, [<Rn>]
+  //
+  // cccc00011001nnnntttt111110011111 where cccc=Cond, tttt=Rt, and nnnn=Rn.
+  constexpr const char *LdrexName = "ldrex";
+  const Type Ty = OpRt->getType();
+  constexpr bool IsLoad = true;
+  constexpr IValueT Rm = RegARM32::Encoded_Reg_pc;
+  emitMemExOp(Cond, Ty, IsLoad, OpRt, Rm, OpAddress, TInfo, LdrexName);
+}
+
 void AssemblerARM32::emitShift(const CondARM32::Cond Cond,
                                const OperandARM32::ShiftKind Shift,
                                const Operand *OpRd, const Operand *OpRm,
                                const Operand *OpSrc1, const bool SetFlags,
                                const char *InstName) {
   constexpr IValueT ShiftOpcode = B3 | B2 | B0; // 1101
   IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
   IValueT Rm = encodeRegister(OpRm, "Rm", InstName);
   IValueT Value;
   switch (encodeOperand(OpSrc1, Value)) {
@@ skipping 194 matching lines @@
   constexpr IValueT SdivOpcode = 0;
   emitDivOp(Cond, SdivOpcode, Rd, Rn, Rm, SdivName);
 }
 
 void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
   constexpr const char *StrName = "str";
   constexpr bool IsLoad = false;
   IValueT Rt = encodeRegister(OpRt, "Rt", StrName);
   const Type Ty = OpRt->getType();
-  switch (typeWidthInBytesLog2(Ty)) {
-  case 3:
-  // STRD is not implemented because target lowering handles i64 and double by
-  // using two (32-bit) store instructions.  Note: Intenionally drop to
-  // default case.
+  switch (Ty) {
+  case IceType_i64:
+    // STRD is not implemented because target lowering handles i64 and double by
+    // using two (32-bit) store instructions.  Note: Intentionally drop to
+    // default case.
+    llvm::report_fatal_error(std::string(StrName) + ": Type " + typeString(Ty) +
+                             " not implemented");
   default:
     llvm::report_fatal_error(std::string(StrName) + ": Type " + typeString(Ty) +
-                             " not implemented");
-  case 0: {
-    // Handles i1 and i8 stores.
-    //
+                             " not allowed");
+  case IceType_i1:
+  case IceType_i8: {
     // STRB (immediate) - ARM section A8.8.207, encoding A1:
     //   strb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
     //   strb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
     //   strb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
     //
     // cccc010pu1w0nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +.
     constexpr bool IsByte = true;
     emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
     return;
   }
-  case 1: {
-    // Handles i16 stores.
-    //
+  case IceType_i16: {
     // STRH (immediate) - ARM section A8.*.217, encoding A1:
     //   strh<c> <Rt>, [<Rn>{, #+/-<Imm8>}]
     //   strh<c> <Rt>, [<Rn>], #+/-<Imm8>
     //   strh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu1w0nnnnttttiiii1011iiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiii=Imm8, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     constexpr const char *Strh = "strh";
     emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh);
     return;
   }
-  case 2: {
+  case IceType_i32: {
     // Note: Handles i32 and float stores. Target lowering handles i64 and
     // double by using two (32 bit) store instructions.
     //
     // STR (immediate) - ARM section A8.8.207, encoding A1:
     //   str<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
     //   str<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
     //   str<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
     //
     // cccc010pu1w0nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +.
     constexpr bool IsByte = false;
     emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
     return;
   }
   }
 }
 
+void AssemblerARM32::strex(const Operand *OpRd, const Operand *OpRt,
+                           const Operand *OpAddress, CondARM32::Cond Cond,
+                           const TargetInfo &TInfo) {
+  // STREXB - ARM section A8.8.213, encoding A1:
+  //   strexb<c> <Rd>, <Rt>, [<Rn>]
+  //
+  // cccc00011100nnnndddd11111001tttt where cccc=Cond, dddd=Rd, tttt=Rt, and
+  // nnnn=Rn.
+  //
+  // STREXH - ARM section A8.8.215, encoding A1:
+  //   strexh<c> <Rd>, <Rt>, [<Rn>]
+  //
+  // cccc00011110nnnndddd11111001tttt where cccc=Cond, dddd=Rd, tttt=Rt, and
+  // nnnn=Rn.
+  //
+  // STREX - ARM section A8.8.212, encoding A1:
+  //   strex<c> <Rd>, <Rt>, [<Rn>]
+  //
+  // cccc00011000nnnndddd11111001tttt where cccc=Cond, dddd=Rd, tttt=Rt, and
+  // nnnn=Rn.
+  //
+  // STREXD - ARM section A8.8.214, encoding A1:
+  //   strexd<c> <Rd>, <Rt>, [<Rn>]
+  //
+  // cccc00011010nnnndddd11111001tttt where cccc=Cond, dddd=Rd, tttt=Rt, and
+  // nnnn=Rn.
+  constexpr const char *StrexName = "strex";
+  // Note: Rt uses Rm shift in encoding.
+  IValueT Rt = encodeRegister(OpRt, "Rt", StrexName);
+  const Type Ty = OpRt->getType();
+  constexpr bool IsLoad = true;
+  emitMemExOp(Cond, Ty, !IsLoad, OpRd, Rt, OpAddress, TInfo, StrexName);
+}
+
 void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ORR (register) - ARM Section A8.8.123, encoding A1:
   //   orr{s}<c> <Rd>, <Rn>, <Rm>
   //
   // cccc0001100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt=ShiftKind,, and s=SetFlags.
   //
   // ORR (register) - ARM Section A8.8.123, encoding A1:
@@ skipping 263 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice