Add various forms of LDREX/STREX to ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 205 matching lines @@
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetInfo &TInfo);
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     ldr(OpRt, OpAddress, Cond, TInfo);
   }
 
+  void ldrex(const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void ldrex(const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    ldrex(OpRt, OpAddress, Cond, TInfo);
+  }
+
   void lsl(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void lsr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
@@ skipping 33 matching lines @@
 
   void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetInfo &TInfo);
 
   void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     str(OpRt, OpAddress, Cond, TInfo);
   }
 
+  void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    strex(OpRd, OpRt, OpAddress, Cond, TInfo);
+  }
+
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   // Implements sxtb/sxth depending on type of OpSrc0.
   void sxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
   void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
@@ skipping 75 matching lines @@
   // Emit ldr/ldrb/str/strb instruction with given address.
   void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
                  const Operand *OpAddress, const TargetInfo &TInfo,
                  const char *InstName);
 
   // Emit ldrh/ldrd/strh/strd instruction with given address using encoding 3.
   void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt,
                      const Operand *OpAddress, const TargetInfo &TInfo,
                      const char *InstName);
 
+  // Emit cccc00011xxlnnnndddd11111001tttt where cccc=Cond, xx encodes type
+  // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt.
+  void emitMemExOp(CondARM32::Cond, Type Ty, bool IsLoad, const Operand *OpRd,
+                   IValueT Rt, const Operand *OpAddress,
+                   const TargetInfo &TInfo, const char *InstName);
+
   // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
   // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
   // rrrrrrrrrrrrrrrr is bitset of Registers.
   void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
                       bool IsLoad, IValueT BaseReg, IValueT Registers,
                       const char *InstName);
 
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
@@ skipping 36 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H