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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 // | 4 // |
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
8 | 8 |
9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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550 EmitMultiMemOp(cond, am, true, base, regs); | 550 EmitMultiMemOp(cond, am, true, base, regs); |
551 } | 551 } |
552 | 552 |
553 // Folded into ARM32::AssemblerARM32::pushList(), since it is its only | 553 // Folded into ARM32::AssemblerARM32::pushList(), since it is its only |
554 // use (and doesn't implement ARM STM instruction). | 554 // use (and doesn't implement ARM STM instruction). |
555 void Assembler::stm(BlockAddressMode am, Register base, RegList regs, | 555 void Assembler::stm(BlockAddressMode am, Register base, RegList regs, |
556 Condition cond) { | 556 Condition cond) { |
557 ASSERT(regs != 0); | 557 ASSERT(regs != 0); |
558 EmitMultiMemOp(cond, am, false, base, regs); | 558 EmitMultiMemOp(cond, am, false, base, regs); |
559 } | 559 } |
560 #endif | |
561 | 560 |
562 | 561 // Moved to ARM::AssemblerARM32::ldrex(); |
563 void Assembler::ldrex(Register rt, Register rn, Condition cond) { | 562 void Assembler::ldrex(Register rt, Register rn, Condition cond) { |
564 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); | 563 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); |
565 ASSERT(rn != kNoRegister); | 564 ASSERT(rn != kNoRegister); |
566 ASSERT(rt != kNoRegister); | 565 ASSERT(rt != kNoRegister); |
567 ASSERT(cond != kNoCondition); | 566 ASSERT(cond != kNoCondition); |
568 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 567 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
569 B24 | | 568 B24 | |
570 B23 | | 569 B23 | |
571 L | | 570 L | |
572 (static_cast<int32_t>(rn) << kLdExRnShift) | | 571 (static_cast<int32_t>(rn) << kLdExRnShift) | |
573 (static_cast<int32_t>(rt) << kLdExRtShift) | | 572 (static_cast<int32_t>(rt) << kLdExRtShift) | |
574 B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; | 573 B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; |
575 Emit(encoding); | 574 Emit(encoding); |
576 } | 575 } |
577 | 576 |
578 | 577 // Moved to ARM::AssemblerARM32::strex(); |
579 void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) { | 578 void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) { |
580 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); | 579 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); |
581 ASSERT(rn != kNoRegister); | 580 ASSERT(rn != kNoRegister); |
582 ASSERT(rd != kNoRegister); | 581 ASSERT(rd != kNoRegister); |
583 ASSERT(rt != kNoRegister); | 582 ASSERT(rt != kNoRegister); |
584 ASSERT(cond != kNoCondition); | 583 ASSERT(cond != kNoCondition); |
585 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 584 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
586 B24 | | 585 B24 | |
587 B23 | | 586 B23 | |
588 (static_cast<int32_t>(rn) << kStrExRnShift) | | 587 (static_cast<int32_t>(rn) << kStrExRnShift) | |
589 (static_cast<int32_t>(rd) << kStrExRdShift) | | 588 (static_cast<int32_t>(rd) << kStrExRdShift) | |
590 B11 | B10 | B9 | B8 | B7 | B4 | | 589 B11 | B10 | B9 | B8 | B7 | B4 | |
591 (static_cast<int32_t>(rt) << kStrExRtShift); | 590 (static_cast<int32_t>(rt) << kStrExRtShift); |
592 Emit(encoding); | 591 Emit(encoding); |
593 } | 592 } |
594 | 593 #endif |
595 | 594 |
596 void Assembler::clrex() { | 595 void Assembler::clrex() { |
597 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); | 596 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE); |
598 int32_t encoding = (kSpecialCondition << kConditionShift) | | 597 int32_t encoding = (kSpecialCondition << kConditionShift) | |
599 B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; | 598 B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; |
600 Emit(encoding); | 599 Emit(encoding); |
601 } | 600 } |
602 | 601 |
603 #if 0 | 602 #if 0 |
604 // Moved to ARM32::AssemblerARM32::nop(). | 603 // Moved to ARM32::AssemblerARM32::nop(). |
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3687 | 3686 |
3688 | 3687 |
3689 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3690 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3691 return fpu_reg_names[reg]; | 3690 return fpu_reg_names[reg]; |
3692 } | 3691 } |
3693 | 3692 |
3694 } // namespace dart | 3693 } // namespace dart |
3695 | 3694 |
3696 #endif // defined TARGET_ARCH_ARM | 3695 #endif // defined TARGET_ARCH_ARM |
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