Subzero: Use "auto" per (unwritten) auto coding style.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 583 matching lines @@
         Load->dump(Func);
         Str << "\n  ";
         Arith->dump(Func);
         Str << "\n  ";
         Store->dump(Func);
         Str << "\n";
       }
       Variable *Beacon = Func->makeVariable(IceType_i32);
       Beacon->setMustNotHaveReg();
       Store->setRmwBeacon(Beacon);
-      InstFakeDef *BeaconDef = InstFakeDef::create(Func, Beacon);
+      auto *BeaconDef = InstFakeDef::create(Func, Beacon);
       Node->getInsts().insert(I3, BeaconDef);
       auto *RMW = Traits::Insts::FakeRMW::create(
           Func, ArithSrcOther, Store->getAddr(), Beacon, Arith->getOp());
       Node->getInsts().insert(I3, RMW);
     }
   }
   if (Func->isVerbose(IceV_RMW))
     Func->getContext()->unlockStr();
 }
 
@@ skipping 82 matching lines @@
           }
         } else if (auto *Select = llvm::dyn_cast<InstSelect>(Next)) {
           Operand *Src0 = Select->getTrueOperand();
           Operand *Src1 = Select->getFalseOperand();
           if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
             NewInst = InstSelect::create(Func, Select->getDest(),
                                          Select->getCondition(), Src0, Src1);
           }
         } else if (auto *Cast = llvm::dyn_cast<InstCast>(Next)) {
           // The load dest can always be folded into a Cast instruction.
-          Variable *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0));
+          auto *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0));
           if (Src0 == LoadDest) {
             NewInst = InstCast::create(Func, Cast->getCastKind(),
                                        Cast->getDest(), LoadSrc);
           }
         }
         if (NewInst) {
           CurInst->setDeleted();
           Next->setDeleted();
           Context.insert(NewInst);
           // Update NewInst->LiveRangesEnded so that target lowering may
@@ skipping 121 matching lines @@
     }
   }
   Type Ty = Arg->getType();
   if (isVectorType(Ty)) {
     InArgsSizeBytes = Traits::applyStackAlignment(InArgsSizeBytes);
   }
   Arg->setStackOffset(BasicFrameOffset + InArgsSizeBytes);
   InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64 || Traits::Is64Bit);
-    typename Traits::X86OperandMem *Mem = Traits::X86OperandMem::create(
+    auto *Mem = Traits::X86OperandMem::create(
         Func, Ty, FramePtr,
         Ctx->getConstantInt32(Arg->getStackOffset() + StackAdjBytes));
     if (isVectorType(Arg->getType())) {
       _movp(Arg, Mem);
     } else {
       _mov(Arg, Mem);
     }
     // This argument-copying instruction uses an explicit Traits::X86OperandMem
     // operand instead of a Variable, so its fill-from-stack operation has to
     // be tracked separately for statistics.
@@ skipping 505 matching lines @@
     case InstArithmetic::Udiv:
     case InstArithmetic::Sdiv:
     case InstArithmetic::Urem:
     case InstArithmetic::Srem:
       llvm::report_fatal_error("Helper call was expected");
       return;
     default:
       break;
     }
 
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     Operand *Src1Lo = loOperand(Src1);
     Operand *Src1Hi = hiOperand(Src1);
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add:
@@ skipping 497 matching lines @@
   if (Dest->isRematerializable()) {
     Context.insert(InstFakeDef::create(Func, Dest));
     return;
   }
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
     Src0 = legalize(Src0);
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
     Operand *Src0Legal;
     if (Dest->hasReg()) {
       // If Dest already has a physical register, then only basic legalization
       // is needed, as the source operand can be a register, immediate, or
@@ skipping 82 matching lines @@
         Constant *ShiftConstant = Ctx->getConstantInt8(ShiftAmount);
         Variable *T = makeReg(DestTy);
         _movp(T, Src0RM);
         _psll(T, ShiftConstant);
         _psra(T, ShiftConstant);
         _movp(Dest, T);
       }
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       // t1=movsx src; t2=t1; t2=sar t2, 31; dst.lo=t1; dst.hi=t2
       Constant *Shift = Ctx->getConstantInt32(31);
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0RM->getType() == IceType_i32) {
         _mov(T_Lo, Src0RM);
       } else if (Src0RM->getType() == IceType_i1) {
         _movzx(T_Lo, Src0RM);
         _shl(T_Lo, Shift);
         _sar(T_Lo, Shift);
       } else {
         _movsx(T_Lo, Src0RM);
       }
@@ skipping 35 matching lines @@
     if (isVectorType(DestTy)) {
       // onemask = materialize(1,1,...); dest = onemask & src
       Variable *OneMask = makeVectorOfOnes(DestTy);
       Variable *T = makeReg(DestTy);
       _movp(T, Src0RM);
       _pand(T, OneMask);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       // t1=movzx src; dst.lo=t1; dst.hi=0
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *Tmp = makeReg(DestLo->getType());
       if (Src0RM->getType() == IceType_i32) {
         _mov(Tmp, Src0RM);
       } else {
         _movzx(Tmp, Src0RM);
       }
       _mov(DestLo, Tmp);
       _mov(DestHi, Zero);
     } else if (Src0RM->getType() == IceType_i1) {
       // t = Src0RM; Dest = t
@@ skipping 182 matching lines @@
       else
         _movzx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   }
   case InstCast::Bitcast: {
     Operand *Src0 = Inst->getSrc(0);
     if (DestTy == Src0->getType()) {
-      InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
+      auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     switch (DestTy) {
     default:
       llvm_unreachable("Unexpected Bitcast dest type");
     case IceType_i8: {
       llvm::report_fatal_error("Helper call was expected");
     } break;
     case IceType_i16: {
@@ skipping 48 matching lines @@
           _movq(Spill, Src0RM);
           SpillLo = Traits::VariableSplit::create(Func, Spill,
                                                   Traits::VariableSplit::Low);
           SpillHi = Traits::VariableSplit::create(Func, Spill,
                                                   Traits::VariableSplit::High);
         } else {
           SpillLo = loOperand(Src0RM);
           SpillHi = hiOperand(Src0RM);
         }
 
-        Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-        Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+        auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+        auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
         Variable *T_Lo = makeReg(IceType_i32);
         Variable *T_Hi = makeReg(IceType_i32);
 
         _mov(T_Lo, SpillLo);
         _mov(DestLo, T_Lo);
         _mov(T_Hi, SpillHi);
         _mov(DestHi, T_Hi);
       }
     } break;
     case IceType_f64: {
@@ skipping 20 matching lines @@
         //   t_hi.i32 = b_hi.i32
         //   hi(s.f64) = t_hi.i32
         //   a.f64 = s.f64
         typename Traits::SpillVariable *SpillVar =
             Func->makeVariable<typename Traits::SpillVariable>(IceType_f64);
         SpillVar->setLinkedTo(Dest);
         Variable *Spill = SpillVar;
         Spill->setMustNotHaveReg();
 
         Variable *T_Lo = nullptr, *T_Hi = nullptr;
-        typename Traits::VariableSplit *SpillLo = Traits::VariableSplit::create(
+        auto *SpillLo = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::Low);
-        typename Traits::VariableSplit *SpillHi = Traits::VariableSplit::create(
+        auto *SpillHi = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::High);
         _mov(T_Lo, loOperand(Src0));
         // Technically, the Spill is defined after the _store happens, but
         // SpillLo is considered a "use" of Spill so define Spill before it is
         // used.
         Context.insert(InstFakeDef::create(Func, Spill));
         _store(T_Lo, SpillLo);
         _mov(T_Hi, hiOperand(Src0));
         _store(T_Hi, SpillHi);
         _movq(Dest, Spill);
@@ skipping 584 matching lines @@
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
     // Expand the element to the appropriate size for it to be inserted in the
     // vector.
     Variable *Expanded = Func->makeVariable(InVectorElementTy);
-    InstCast *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
-                                      ElementToInsertNotLegalized);
+    auto *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
+                                  ElementToInsertNotLegalized);
     lowerCast(Cast);
     ElementToInsertNotLegalized = Expanded;
   }
 
   if (Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
       InstructionSet >= Traits::SSE4_1) {
     // Use insertps, pinsrb, pinsrw, or pinsrd.
     Operand *ElementRM =
         legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
     Operand *SourceVectRM =
@@ skipping 133 matching lines @@
     // fence (both atomic and non-atomic). The InstX8632Mfence instruction is
     // currently marked coarsely as "HasSideEffects".
     _mfence();
     return;
   case Intrinsics::AtomicIsLockFree: {
     // X86 is always lock free for 8/16/32/64 bit accesses.
     // TODO(jvoung): Since the result is constant when given a constant byte
     // size, this opens up DCE opportunities.
     Operand *ByteSize = Instr->getArg(0);
     Variable *Dest = Instr->getDest();
-    if (ConstantInteger32 *CI = llvm::dyn_cast<ConstantInteger32>(ByteSize)) {
+    if (auto *CI = llvm::dyn_cast<ConstantInteger32>(ByteSize)) {
       Constant *Result;
       switch (CI->getValue()) {
       default:
         // Some x86-64 processors support the cmpxchg16b instruction, which can
         // make 16-byte operations lock free (when used with the LOCK prefix).
         // However, that's not supported in 32-bit mode, so just return 0 even
         // for large sizes.
         Result = Ctx->getConstantZero(IceType_i32);
         break;
       case 1:
@@ skipping 24 matching lines @@
         // Follow what GCC does and use a movq instead of what lowerLoad()
         // normally does (split the load into two). Thus, this skips
         // load/arithmetic op folding. Load/arithmetic folding can't happen
         // anyway, since this is x86-32 and integer arithmetic only happens on
         // 32-bit quantities.
         Variable *T = makeReg(IceType_f64);
         typename Traits::X86OperandMem *Addr =
             formMemoryOperand(Instr->getArg(0), IceType_f64);
         _movq(T, Addr);
         // Then cast the bits back out of the XMM register to the i64 Dest.
-        InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
+        auto *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
         lowerCast(Cast);
         // Make sure that the atomic load isn't elided when unused.
         Context.insert(InstFakeUse::create(Func, Dest64On32->getLo()));
         Context.insert(InstFakeUse::create(Func, Dest64On32->getHi()));
         return;
       }
     }
-    InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
+    auto *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
     lowerLoad(Load);
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
     // Since lowerLoad may fuse the load w/ an arithmetic instruction, insert
     // the FakeUse on the last-inserted instruction's dest.
     Context.insert(
         InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::isMemoryOrderValid(
@@ skipping 16 matching lines @@
     // We require the memory address to be naturally aligned. Given that is the
     // case, then normal stores are atomic. Add a fence after the store to make
     // it visible.
     Operand *Value = Instr->getArg(0);
     Operand *Ptr = Instr->getArg(1);
     if (!Traits::Is64Bit && Value->getType() == IceType_i64) {
       // Use a movq instead of what lowerStore() normally does (split the store
       // into two), following what GCC does. Cast the bits from int -> to an
       // xmm register first.
       Variable *T = makeReg(IceType_f64);
-      InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, T, Value);
+      auto *Cast = InstCast::create(Func, InstCast::Bitcast, T, Value);
       lowerCast(Cast);
       // Then store XMM w/ a movq.
       typename Traits::X86OperandMem *Addr =
           formMemoryOperand(Ptr, IceType_f64);
       _storeq(T, Addr);
       _mfence();
       return;
     }
-    InstStore *Store = InstStore::create(Func, Value, Ptr);
+    auto *Store = InstStore::create(Func, Value, Ptr);
     lowerStore(Store);
     _mfence();
     return;
   }
   case Intrinsics::Bswap: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
     // In 32-bit mode, bswap only works on 32-bit arguments, and the argument
     // must be a register. Use rotate left for 16-bit bswap.
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
       Variable *T_Lo = legalizeToReg(loOperand(Val));
       Variable *T_Hi = legalizeToReg(hiOperand(Val));
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _bswap(T_Lo);
       _bswap(T_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else if ((Traits::Is64Bit && Val->getType() == IceType_i64) ||
                Val->getType() == IceType_i32) {
       Variable *T = legalizeToReg(Val);
       _bswap(T);
       _mov(Dest, T);
     } else {
@@ skipping 34 matching lines @@
     Call->addArg(Val);
     lowerCall(Call);
     // The popcount helpers always return 32-bit values, while the intrinsic's
     // signature matches the native POPCNT instruction and fills a 64-bit reg
     // (in 64-bit mode). Thus, clear the upper bits of the dest just in case
     // the user doesn't do that in the IR. If the user does that in the IR,
     // then this zero'ing instruction is dead and gets optimized out.
     if (!Traits::Is64Bit) {
       assert(T == Dest);
       if (Val->getType() == IceType_i64) {
-        Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+        auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
         _mov(DestHi, Zero);
       }
     } else {
       assert(Val->getType() == IceType_i64);
       // T is 64 bit. It needs to be copied to dest. We need to:
       //
       // T_1.32 = trunc T.64 to i32
       // T_2.64 = zext T_1.32 to i64
       // Dest.<<right_size>> = T_2.<<right_size>>
@@ skipping 148 matching lines @@
     Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
     Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
     typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
     constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
-    Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
+    auto *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   int32_t Eax;
   switch (Ty) {
   default:
     llvm_unreachable("Bad type for cmpxchg");
   // fallthrough
   case IceType_i32:
@@ skipping 40 matching lines @@
   // This assumes that the atomic cmpxchg has not been lowered yet,
   // so that the instructions seen in the scan from "Cur" is simple.
   assert(llvm::isa<InstIntrinsicCall>(*I));
   Inst *NextInst = Context.getNextInst(I);
   if (!NextInst)
     return false;
   // There might be phi assignments right before the compare+branch, since this
   // could be a backward branch for a loop. This placement of assignments is
   // determined by placePhiStores().
   std::vector<InstAssign *> PhiAssigns;
-  while (InstAssign *PhiAssign = llvm::dyn_cast<InstAssign>(NextInst)) {
+  while (auto *PhiAssign = llvm::dyn_cast<InstAssign>(NextInst)) {
     if (PhiAssign->getDest() == Dest)
       return false;
     PhiAssigns.push_back(PhiAssign);
     NextInst = Context.getNextInst(I);
     if (!NextInst)
       return false;
   }
-  if (InstIcmp *NextCmp = llvm::dyn_cast<InstIcmp>(NextInst)) {
+  if (auto *NextCmp = llvm::dyn_cast<InstIcmp>(NextInst)) {
     if (!(NextCmp->getCondition() == InstIcmp::Eq &&
           ((NextCmp->getSrc(0) == Dest && NextCmp->getSrc(1) == Expected) ||
            (NextCmp->getSrc(1) == Dest && NextCmp->getSrc(0) == Expected)))) {
       return false;
     }
     NextInst = Context.getNextInst(I);
     if (!NextInst)
       return false;
-    if (InstBr *NextBr = llvm::dyn_cast<InstBr>(NextInst)) {
+    if (auto *NextBr = llvm::dyn_cast<InstBr>(NextInst)) {
       if (!NextBr->isUnconditional() &&
           NextCmp->getDest() == NextBr->getCondition() &&
           NextBr->isLastUse(NextCmp->getDest())) {
         lowerAtomicCmpxchg(Dest, PtrToMem, Expected, Desired);
         for (size_t i = 0; i < PhiAssigns.size(); ++i) {
           // Lower the phi assignments now, before the branch (same placement
           // as before).
           InstAssign *PhiAssign = PhiAssigns[i];
           PhiAssign->setDeleted();
           lowerAssign(PhiAssign);
@@ skipping 157 matching lines @@
       _mov(T_ebx, loOperand(Val));
       _mov(T_ecx, hiOperand(Val));
       Context.insert(Label);
     }
     constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     _br(Traits::Cond::Br_ne, Label);
     if (!IsXchg8b) {
       // If Val is a variable, model the extended live range of Val through
       // the end of the loop, since it will be re-used by the loop.
-      if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
-        Variable *ValLo = llvm::cast<Variable>(loOperand(ValVar));
-        Variable *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
+      if (auto *ValVar = llvm::dyn_cast<Variable>(Val)) {
+        auto *ValLo = llvm::cast<Variable>(loOperand(ValVar));
+        auto *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
         Context.insert(InstFakeUse::create(Func, ValLo));
         Context.insert(InstFakeUse::create(Func, ValHi));
       }
     } else {
       // For xchg, the loop is slightly smaller and ebx/ecx are used.
       Context.insert(InstFakeUse::create(Func, T_ebx));
       Context.insert(InstFakeUse::create(Func, T_ecx));
     }
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
       Context.insert(InstFakeUse::create(Func, Base));
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   int32_t Eax;
   switch (Ty) {
   default:
     llvm_unreachable("Bad type for atomicRMW");
   // fallthrough
@@ skipping 15 matching lines @@
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
   _br(Traits::Cond::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
-  if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
+  if (auto *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert(InstFakeUse::create(Func, ValVar));
   }
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
     Context.insert(InstFakeUse::create(Func, Base));
   _mov(Dest, T_eax);
 }
 
 /// Lowers count {trailing, leading} zeros intrinsic.
 ///
@@ skipping 49 matching lines @@
   }
   _cmov(T_Dest, T, Traits::Cond::Br_ne);
   if (!Cttz) {
     _xor(T_Dest, ThirtyOne);
   }
   if (Traits::Is64Bit || Ty == IceType_i32) {
     _mov(Dest, T_Dest);
     return;
   }
   _add(T_Dest, ThirtyTwo);
-  Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-  Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+  auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+  auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
   Variable *SecondVar = legalizeToReg(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
@@ skipping 700 matching lines @@
 void TargetX86Base<Machine>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
   // the source operand is transformed into an Traits::X86OperandMem operand.
   // Note that the address mode optimization already creates an
   // Traits::X86OperandMem operand, so it doesn't need another level of
   // transformation.
   Variable *DestLoad = Load->getDest();
   Type Ty = DestLoad->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   doMockBoundsCheck(Src0);
-  InstAssign *Assign = InstAssign::create(Func, DestLoad, Src0);
+  auto *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
 template <class Machine> void TargetX86Base<Machine>::doAddressOptLoad() {
   Inst *Inst = Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
@@ skipping 145 matching lines @@
   // instruction doesn't allow an immediate operand:
   // mov t, SrcT; cmov_!cond t, SrcF; mov dest, t
   if (llvm::isa<Constant>(SrcT) && !llvm::isa<Constant>(SrcF)) {
     std::swap(SrcT, SrcF);
     Cond = InstX86Base<Machine>::getOppositeCondition(Cond);
   }
   if (!Traits::Is64Bit && DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *TLo = nullptr;
     Operand *SrcFLo = legalize(loOperand(SrcF));
     _mov(TLo, SrcFLo);
     Operand *SrcTLo = legalize(loOperand(SrcT), Legal_Reg | Legal_Mem);
     _cmov(TLo, SrcTLo, Cond);
     _mov(DestLo, TLo);
     // Set the high portion.
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *THi = nullptr;
     Operand *SrcFHi = legalize(hiOperand(SrcF));
     _mov(THi, SrcFHi);
     Operand *SrcTHi = legalize(hiOperand(SrcT), Legal_Reg | Legal_Mem);
     _cmov(THi, SrcTHi, Cond);
     _mov(DestHi, THi);
     return;
   }
 
   assert(DestTy == IceType_i16 || DestTy == IceType_i32 ||
@@ skipping 25 matching lines @@
            llvm::cast<typename Traits::X86OperandMem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     _storep(legalizeToReg(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
 template <class Machine> void TargetX86Base<Machine>::doAddressOptStore() {
-  InstStore *Inst = llvm::cast<InstStore>(Context.getCur());
+  auto *Inst = llvm::cast<InstStore>(Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0;
   auto *Base = llvm::dyn_cast<Variable>(Addr);
   // Vanilla ICE store instructions should not use the segment registers, and
   // computeAddressOpt only works at the level of Variables and Constants, not
   // other Traits::X86OperandMem, so there should be no mention of segment
   // registers there either.
   const typename Traits::X86OperandMem::SegmentRegisters SegmentReg =
       Traits::X86OperandMem::DefaultSegment;
   if (computeAddressOpt(Func, Inst, Relocatable, Offset, Base, Index, Shift)) {
     Inst->setDeleted();
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
     Addr = Traits::X86OperandMem::create(Func, Data->getType(), Base, OffsetOp,
                                          Index, Shift, SegmentReg);
-    InstStore *NewStore = InstStore::create(Func, Data, Addr);
+    auto *NewStore = InstStore::create(Func, Data, Addr);
     if (Inst->getDest())
       NewStore->setRmwBeacon(Inst->getRmwBeacon());
     Context.insert(NewStore);
   }
 }
 
 template <class Machine>
 Operand *TargetX86Base<Machine>::lowerCmpRange(Operand *Comparison,
                                                uint64_t Min, uint64_t Max) {
   // TODO(ascull): 64-bit should not reach here but only because it is not
@@ skipping 265 matching lines @@
 ///
 ///   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
 ///   %cmp.ext = sext <n x i1> %cmp to <n x ty>
 ///
 /// We can eliminate the sext operation by copying the result of pcmpeqd,
 /// pcmpgtd, or cmpps (which produce sign extended results) to the result of the
 /// sext operation.
 template <class Machine>
 void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
     Variable *SignExtendedResult) {
-  if (InstCast *NextCast =
+  if (auto *NextCast =
           llvm::dyn_cast_or_null<InstCast>(Context.getNextInst())) {
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
@@ skipping 654 matching lines @@
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
         Variable *V = copyToReg(Const, RegNum);
         return V;
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
-    if (ConstantInteger32 *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
+    if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
     }
 
     // Convert a scalar floating point constant into an explicit memory
     // operand.
     if (isScalarFloatingType(Ty)) {
       if (auto *ConstFloat = llvm::dyn_cast<ConstantFloat>(Const)) {
@@ skipping 104 matching lines @@
 
 template <class Machine>
 typename TargetX86Base<Machine>::Traits::X86OperandMem *
 TargetX86Base<Machine>::formMemoryOperand(Operand *Opnd, Type Ty,
                                           bool DoLegalize) {
   auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Opnd);
   // It may be the case that address mode optimization already creates an
   // Traits::X86OperandMem, so in that case it wouldn't need another level of
   // transformation.
   if (!Mem) {
-    Variable *Base = llvm::dyn_cast<Variable>(Opnd);
-    Constant *Offset = llvm::dyn_cast<Constant>(Opnd);
+    auto *Base = llvm::dyn_cast<Variable>(Opnd);
+    auto *Offset = llvm::dyn_cast<Constant>(Opnd);
     assert(Base || Offset);
     if (Offset) {
       // During memory operand building, we do not blind or pool the constant
       // offset, we will work on the whole memory operand later as one entity
       // later, this save one instruction. By turning blinding and pooling off,
       // we guarantee legalize(Offset) will return a Constant*.
       {
         BoolFlagSaver B(RandomizationPoolingPaused, true);
 
         Offset = llvm::cast<Constant>(legalize(Offset));
@@ skipping 127 matching lines @@
       // TO:
       //  insert: mov imm+cookie, Reg
       //  insert: lea -cookie[Reg], Reg
       //  => Reg
       // If we have already assigned a phy register, we must come from
       // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
       // assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here. Note we use 'lea' instruction
       // instead of 'xor' to avoid affecting the flags.
       Variable *Reg = makeReg(IceType_i32, RegNum);
-      ConstantInteger32 *Integer = llvm::cast<ConstantInteger32>(Immediate);
+      auto *Integer = llvm::cast<ConstantInteger32>(Immediate);
       uint32_t Value = Integer->getValue();
       uint32_t Cookie = Func->getConstantBlindingCookie();
       _mov(Reg, Ctx->getConstantInt(IceType_i32, Cookie + Value));
       Constant *Offset = Ctx->getConstantInt(IceType_i32, 0 - Cookie);
       _lea(Reg, Traits::X86OperandMem::create(Func, IceType_i32, Reg, Offset,
                                               nullptr, 0));
       if (Immediate->getType() != IceType_i32) {
         Variable *TruncReg = makeReg(Immediate->getType(), RegNum);
         _mov(TruncReg, Reg);
         return TruncReg;
@@ skipping 42 matching lines @@
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
   // If this memory operand is already a randomized one, we do not randomize it
   // again.
   if (MemOperand->getRandomized())
     return MemOperand;
 
-  if (Constant *C = llvm::dyn_cast_or_null<Constant>(MemOperand->getOffset())) {
+  if (auto *C = llvm::dyn_cast_or_null<Constant>(MemOperand->getOffset())) {
     if (C->shouldBeRandomizedOrPooled(Ctx)) {
       // The offset of this mem operand should be blinded or pooled
       Ctx->statsUpdateRPImms();
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
           RPI_Randomize) {
         // blind the constant offset
         // FROM:
         //  offset[base, index, shift]
         // TO:
         //  insert: lea offset+cookie[base], RegTemp
@@ skipping 81 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H