Subzero: Use "auto" per (unwritten) auto coding style.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 744 matching lines @@
   if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 uint32_t TargetARM32::getStackAlignment() const {
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
-  if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) {
+  if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 const char *RegARM32::RegNames[] = {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
   name,
     REGARM32_TABLE
@@ skipping 1160 matching lines @@
     break;
   }
   case IceType_i64: {
     Variable *T = makeReg(IceType_i32);
     _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex));
     // T isn't going to be used, but we need the side-effect of setting flags
     // from this operation.
     Context.insert(InstFakeUse::create(Func, T));
   }
   }
-  InstARM32Label *Label = InstARM32Label::create(Func, this);
+  auto *Label = InstARM32Label::create(Func, this);
   _br(Label, CondARM32::NE);
   _trap();
   Context.insert(Label);
 }
 
 void TargetARM32::lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R,
                                Operand *Src1, ExtInstr ExtFunc,
                                DivInstr DivFunc, bool IsRemainder) {
   div0Check(Dest->getType(), Src1, nullptr);
   Variable *Src1R = legalizeToReg(Src1);
@@ skipping 249 matching lines @@
 }
 
 void TargetARM32::lowerInt64Arithmetic(InstArithmetic::OpKind Op,
                                        Variable *Dest, Operand *Src0,
                                        Operand *Src1) {
   Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
   Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
   assert(SrcsLo.swappedOperands() == SrcsHi.swappedOperands());
   assert(SrcsLo.hasConstOperand() == SrcsHi.hasConstOperand());
 
-  Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-  Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+  auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+  auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   Variable *T_Lo = makeReg(DestLo->getType());
   Variable *T_Hi = makeReg(DestHi->getType());
 
   switch (Op) {
   case InstArithmetic::_num:
     llvm::report_fatal_error("Unknown arithmetic operator");
     return;
   case InstArithmetic::Add: {
     Variable *Src0LoR = SrcsLo.src0R(this);
     Operand *Src1LoRF = SrcsLo.src1RF(this);
@@ skipping 1201 matching lines @@
     return;
   case InstCast::Sext: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
       Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() != IceType_i1) {
         Variable *Src0R = legalizeToReg(Src0);
         _sxt(T_Lo, Src0R);
       } else {
         Operand *_0 = Ctx->getConstantZero(IceType_i32);
         Operand *_m1 = Ctx->getConstantInt32(-1);
@@ skipping 27 matching lines @@
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
       Variable *T = makeReg(Dest->getType());
       Context.insert(InstFakeDef::create(Func, T, legalizeToReg(Src0)));
       _mov(Dest, T);
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Operand *_0 =
           legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
 
       switch (Src0->getType()) {
       default: {
         assert(Src0->getType() != IceType_i64);
         _uxt(T_Lo, legalizeToReg(Src0));
       } break;
       case IceType_i32: {
         _mov(T_Lo, legalize(Src0, Legal_Reg | Legal_Flex));
       } break;
@@ skipping 147 matching lines @@
         DestIsF32
             ? (SourceIsSigned ? InstARM32Vcvt::Si2s : InstARM32Vcvt::Ui2s)
             : (SourceIsSigned ? InstARM32Vcvt::Si2d : InstARM32Vcvt::Ui2d);
     _vcvt(T, Src0R, Conversion);
     _mov(Dest, T);
     break;
   }
   case InstCast::Bitcast: {
     Operand *Src0 = Inst->getSrc(0);
     if (Dest->getType() == Src0->getType()) {
-      InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
+      auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     Type DestType = Dest->getType();
     switch (DestType) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Unexpected bitcast.");
     case IceType_i1:
       UnimplementedError(Func->getContext()->getFlags());
@@ skipping 353 matching lines @@
   Int32Operands Srcs(Src0, Src1);
   const int32_t ShAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShAmt >= 0);
 
   if (!Srcs.hasConstOperand()) {
     Variable *Src0R = makeReg(IceType_i32);
     Operand *ShAmtImm = shAmtImm(ShAmt);
     _lsl(Src0R, legalizeToReg(Src0), ShAmtImm);
 
     Variable *Src1R = legalizeToReg(Src1);
-    OperandARM32FlexReg *Src1F = OperandARM32FlexReg::create(
-        Func, IceType_i32, Src1R, OperandARM32::LSL, ShAmtImm);
+    auto *Src1F = OperandARM32FlexReg::create(Func, IceType_i32, Src1R,
+                                              OperandARM32::LSL, ShAmtImm);
     _cmp(Src0R, Src1F);
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   const int32_t Value = Srcs.getConstantValue();
   if ((Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) && Value == 0) {
     Operand *ShAmtImm = shAmtImm(ShAmt);
     Variable *T = makeReg(IceType_i32);
     _lsls(T, Srcs.src0R(this), ShAmtImm);
     Context.insert(InstFakeUse::create(Func, T));
@@ skipping 126 matching lines @@
   Variable *PtrContentsLoReg;
   Variable *Value = Func->makeVariable(DestTy);
   Variable *ValueReg;
   Variable *ValueHiReg;
   Variable *ValueLoReg;
   Variable *Success = makeReg(IceType_i32);
   Variable *TmpReg;
   Variable *TmpHiReg;
   Variable *TmpLoReg;
   Operand *_0 = Ctx->getConstantZero(IceType_i32);
-  InstARM32Label *Retry = InstARM32Label::create(Func, this);
+  auto *Retry = InstARM32Label::create(Func, this);
 
   if (DestTy == IceType_i64) {
     Variable64On32 *PtrContentsReg64 = makeI64RegPair();
     PtrContentsHiReg = PtrContentsReg64->getHi();
     PtrContentsLoReg = PtrContentsReg64->getLo();
     PtrContentsReg = PtrContentsReg64;
 
     llvm::cast<Variable64On32>(Value)->initHiLo(Func);
     Variable64On32 *ValueReg64 = makeI64RegPair();
     ValueHiReg = ValueReg64->getHi();
@@ skipping 119 matching lines @@
 
 void TargetARM32::postambleCtpop64(const InstCall *Instr) {
   Operand *Arg0 = Instr->getArg(0);
   if (isInt32Asserting32Or64(Arg0->getType())) {
     return;
   }
   // The popcount helpers always return 32-bit values, while the intrinsic's
   // signature matches some 64-bit platform's native instructions and expect to
   // fill a 64-bit reg. Thus, clear the upper bits of the dest just in case the
   // user doesn't do that in the IR or doesn't toss the bits via truncate.
-  Variable *DestHi = llvm::cast<Variable>(hiOperand(Instr->getDest()));
+  auto *DestHi = llvm::cast<Variable>(hiOperand(Instr->getDest()));
   Variable *T = makeReg(IceType_i32);
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   _mov(T, _0);
   _mov(DestHi, T);
 }
 
 void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   Variable *Dest = Instr->getDest();
   Type DestTy = (Dest != nullptr) ? Dest->getType() : IceType_void;
@@ skipping 81 matching lines @@
       //
       // The fake-use is needed to prevent those variables from being clobbered
       // in the loop (which will happen under register pressure.)
       Variable64On32 *Tmp = makeI64RegPair();
       Variable64On32 *ValueVar =
           llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       Variable *AddrVar = makeReg(IceType_i32);
       Variable *Success = makeReg(IceType_i32);
       OperandARM32Mem *Mem;
       Operand *_0 = Ctx->getConstantZero(IceType_i32);
-      InstARM32Label *Retry = InstARM32Label::create(Func, this);
+      auto *Retry = InstARM32Label::create(Func, this);
       Variable64On32 *NewReg = makeI64RegPair();
       ValueVar->initHiLo(Func);
       ValueVar->mustNotHaveReg();
 
       _dmb();
       lowerAssign(InstAssign::create(Func, ValueVar, Value));
       lowerAssign(InstAssign::create(Func, AddrVar, Addr));
 
       Context.insert(Retry);
       Context.insert(InstFakeDef::create(Func, NewReg));
@@ skipping 70 matching lines @@
       Func->setError("Unexpected memory ordering for AtomicCmpxchg");
       return;
     }
 
     OperandARM32Mem *Mem;
     Variable *TmpReg;
     Variable *Expected, *ExpectedReg;
     Variable *New, *NewReg;
     Variable *Success = makeReg(IceType_i32);
     Operand *_0 = Ctx->getConstantZero(IceType_i32);
-    InstARM32Label *Retry = InstARM32Label::create(Func, this);
+    auto *Retry = InstARM32Label::create(Func, this);
 
     if (DestTy == IceType_i64) {
       Variable64On32 *TmpReg64 = makeI64RegPair();
       Variable64On32 *New64 =
           llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       Variable64On32 *NewReg64 = makeI64RegPair();
       Variable64On32 *Expected64 =
           llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       Variable64On32 *ExpectedReg64 = makeI64RegPair();
 
@@ skipping 90 matching lines @@
   }
   case Intrinsics::Bswap: {
     Operand *Val = Instr->getArg(0);
     Type Ty = Val->getType();
     if (Ty == IceType_i64) {
       Val = legalizeUndef(Val);
       Variable *Val_Lo = legalizeToReg(loOperand(Val));
       Variable *Val_Hi = legalizeToReg(hiOperand(Val));
       Variable *T_Lo = makeReg(IceType_i32);
       Variable *T_Hi = makeReg(IceType_i32);
-      Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-      Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _rev(T_Lo, Val_Lo);
       _rev(T_Hi, Val_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else {
       assert(Ty == IceType_i32 || Ty == IceType_i16);
       Variable *ValR = legalizeToReg(Val);
       Variable *T = makeReg(Ty);
       _rev(T, ValR);
       if (Val->getType() == IceType_i16) {
@@ skipping 112 matching lines @@
   }
   return;
 }
 
 void TargetARM32::lowerCLZ(Variable *Dest, Variable *ValLoR, Variable *ValHiR) {
   Type Ty = Dest->getType();
   assert(Ty == IceType_i32 || Ty == IceType_i64);
   Variable *T = makeReg(IceType_i32);
   _clz(T, ValLoR);
   if (Ty == IceType_i64) {
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *Zero =
         legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
     Operand *ThirtyTwo =
         legalize(Ctx->getConstantInt32(32), Legal_Reg | Legal_Flex);
     _cmp(ValHiR, Zero);
     Variable *T2 = makeReg(IceType_i32);
     _add(T2, T, ThirtyTwo);
     _clz(T2, ValHiR, CondARM32::NE);
     // T2 is actually a source as well when the predicate is not AL (since it
     // may leave T2 alone). We use _set_dest_redefined to prolong the liveness
@@ skipping 11 matching lines @@
 
 void TargetARM32::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
   // the source operand is transformed into an OperandARM32Mem operand.
   Type Ty = Load->getDest()->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   Variable *DestLoad = Load->getDest();
 
   // TODO(jvoung): handled folding opportunities. Sign and zero extension can
   // be folded into a load.
-  InstAssign *Assign = InstAssign::create(Func, DestLoad, Src0);
+  auto *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
 namespace {
 void dumpAddressOpt(const Cfg *Func, const Variable *Base, int32_t Offset,
                     const Variable *OffsetReg, int16_t OffsetRegShAmt,
                     const Inst *Reason) {
   if (!BuildDefs::dump())
     return;
   if (!Func->isVerbose(IceV_AddrOpt))
@@ skipping 816 matching lines @@
     // being lowered is a 64 bit value, then the result should be split and the
     // lo and hi components will need to go in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
 
 OperandARM32Mem *TargetARM32::formMemoryOperand(Operand *Operand, Type Ty) {
-  OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
+  auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
   // It may be the case that address mode optimization already creates an
   // OperandARM32Mem, so in that case it wouldn't need another level of
   // transformation.
   if (Mem) {
     return llvm::cast<OperandARM32Mem>(legalize(Mem));
   }
   // If we didn't do address mode optimization, then we only have a
   // base/offset to work with. ARM always requires a base register, so
   // just use that to hold the operand.
-  Variable *Base = llvm::cast<Variable>(
+  auto *Base = llvm::cast<Variable>(
       legalize(Operand, Legal_Reg | Legal_Rematerializable));
   return OperandARM32Mem::create(
       Func, Ty, Base,
       llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));
 }
 
 Variable64On32 *TargetARM32::makeI64RegPair() {
   Variable64On32 *Reg =
       llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
   Reg->setMustHaveReg();
@@ skipping 785 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice