Add the RSC instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1593 matching lines @@
   //   rsb{s}<c> <Rd>, <Rn>, <Rm>{, <Shift>}
   //
   // cccc0000011snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt==ShiftKind, and s=SetFlags.
   constexpr const char *RsbName = "rsb";
   constexpr IValueT RsbOpcode = B1 | B0; // 0011
   emitType01(Cond, RsbOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              RsbName);
 }
 
+void AssemblerARM32::rsc(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  // RSC (immediate) - ARM section A8.8.155, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
+  //
+  // cccc0010111snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
+  //
+  // RSC (register) - ARM section A8.8.156, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+  //
+  // cccc0000111snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
+  //
+  // RSC (register-shifted register) - ARM section A8.8.157, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
+  //
+  // cccc0000111fnnnnddddssss0tt1mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, ssss=Rs, tt defined <type>, and f=SetFlags.
+  constexpr const char *RscName = "rsc";
+  constexpr IValueT RscOpcode = B2 | B1 | B0; // i.e. 0111.
+  emitType01(Cond, RscOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
+             RscName);
+}
+
 void AssemblerARM32::sxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *SxtName = "sxt";
   constexpr IValueT SxtOpcode = B26 | B25 | B23 | B21;
   emitSignExtend(Cond, SxtOpcode, OpRd, OpSrc0, SxtName);
 }
 
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SUB (register) - ARM section A8.8.223, encoding A1:
   //   sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   // SUB (SP minus register): See ARM section 8.8.226, encoding A1:
   //   sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
   //
   // cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
   //
   // Sub (Immediate) - ARM section A8.8.222, encoding A1:
   //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
-  // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
+  // Sub (Sp minus immediate) - ARM section A8.8.225, encoding A1:
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
   constexpr const char *SubName = "sub";
   constexpr IValueT SubOpcode = B1; // 0010
   emitType01(Cond, SubOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              SubName);
 }
 
@@ skipping 59 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice