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Side by Side Diff: src/ppc/constants-ppc.h

Issue 1515603002: PPC64: [turbofan] Changed TruncateFloat64ToInt64 to TryTruncateFloat64ToInt64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_PPC_CONSTANTS_PPC_H_ 5 #ifndef V8_PPC_CONSTANTS_PPC_H_
6 #define V8_PPC_CONSTANTS_PPC_H_ 6 #define V8_PPC_CONSTANTS_PPC_H_
7 7
8 #include <stdint.h> 8 #include <stdint.h>
9 9
10 #include "src/base/logging.h" 10 #include "src/base/logging.h"
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272 FSEL = 23 << 1, // Floating Select 272 FSEL = 23 << 1, // Floating Select
273 FMUL = 25 << 1, // Floating Multiply 273 FMUL = 25 << 1, // Floating Multiply
274 FMSUB = 28 << 1, // Floating Multiply-Subtract 274 FMSUB = 28 << 1, // Floating Multiply-Subtract
275 FMADD = 29 << 1, // Floating Multiply-Add 275 FMADD = 29 << 1, // Floating Multiply-Add
276 276
277 // Bits 10-1 277 // Bits 10-1
278 FCMPU = 0 << 1, // Floating Compare Unordered 278 FCMPU = 0 << 1, // Floating Compare Unordered
279 FRSP = 12 << 1, // Floating-Point Rounding 279 FRSP = 12 << 1, // Floating-Point Rounding
280 FCTIW = 14 << 1, // Floating Convert to Integer Word X-form 280 FCTIW = 14 << 1, // Floating Convert to Integer Word X-form
281 FCTIWZ = 15 << 1, // Floating Convert to Integer Word with Round to Zero 281 FCTIWZ = 15 << 1, // Floating Convert to Integer Word with Round to Zero
282 MTFSB1 = 38 << 1, // Move to FPSCR Bit 1
282 FNEG = 40 << 1, // Floating Negate 283 FNEG = 40 << 1, // Floating Negate
283 MCRFS = 64 << 1, // Move to Condition Register from FPSCR 284 MCRFS = 64 << 1, // Move to Condition Register from FPSCR
285 MTFSB0 = 70 << 1, // Move to FPSCR Bit 0
284 FMR = 72 << 1, // Floating Move Register 286 FMR = 72 << 1, // Floating Move Register
285 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate 287 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate
286 FABS = 264 << 1, // Floating Absolute Value 288 FABS = 264 << 1, // Floating Absolute Value
287 FRIN = 392 << 1, // Floating Round to Integer Nearest 289 FRIN = 392 << 1, // Floating Round to Integer Nearest
288 FRIZ = 424 << 1, // Floating Round to Integer Toward Zero 290 FRIZ = 424 << 1, // Floating Round to Integer Toward Zero
289 FRIP = 456 << 1, // Floating Round to Integer Plus 291 FRIP = 456 << 1, // Floating Round to Integer Plus
290 FRIM = 488 << 1, // Floating Round to Integer Minus 292 FRIM = 488 << 1, // Floating Round to Integer Minus
291 MFFS = 583 << 1, // move from FPSCR x-form 293 MFFS = 583 << 1, // move from FPSCR x-form
292 MTFSF = 711 << 1, // move to FPSCR fields XFL-form 294 MTFSF = 711 << 1, // move to FPSCR fields XFL-form
293 FCTID = 814 << 1, // Floating convert to integer doubleword 295 FCTID = 814 << 1, // Floating convert to integer doubleword
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395 #undef CR_LT 397 #undef CR_LT
396 #undef CR_GT 398 #undef CR_GT
397 #undef CR_EQ 399 #undef CR_EQ
398 #undef CR_SO 400 #undef CR_SO
399 #endif 401 #endif
400 402
401 enum CRBit { CR_LT = 0, CR_GT = 1, CR_EQ = 2, CR_SO = 3, CR_FU = 3 }; 403 enum CRBit { CR_LT = 0, CR_GT = 1, CR_EQ = 2, CR_SO = 3, CR_FU = 3 };
402 404
403 #define CRWIDTH 4 405 #define CRWIDTH 4
404 406
407 // These are the documented bit positions biased down by 32
408 enum FPSCRBit {
409 VXSOFT = 21, // 53: Software-Defined Condition
410 VXSQRT = 22, // 54: Invalid Square Root
411 VXCVI = 23 // 55: Invalid Integer Convert
412 };
413
405 // ----------------------------------------------------------------------------- 414 // -----------------------------------------------------------------------------
406 // Supervisor Call (svc) specific support. 415 // Supervisor Call (svc) specific support.
407 416
408 // Special Software Interrupt codes when used in the presence of the PPC 417 // Special Software Interrupt codes when used in the presence of the PPC
409 // simulator. 418 // simulator.
410 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 419 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
411 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 420 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
412 enum SoftwareInterruptCodes { 421 enum SoftwareInterruptCodes {
413 // transition to C code 422 // transition to C code
414 kCallRtRedirected = 0x10, 423 kCallRtRedirected = 0x10,
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581 // Lookup the register number for the name provided. 590 // Lookup the register number for the name provided.
582 static int Number(const char* name); 591 static int Number(const char* name);
583 592
584 private: 593 private:
585 static const char* names_[kNumDoubleRegisters]; 594 static const char* names_[kNumDoubleRegisters];
586 }; 595 };
587 } // namespace internal 596 } // namespace internal
588 } // namespace v8 597 } // namespace v8
589 598
590 #endif // V8_PPC_CONSTANTS_PPC_H_ 599 #endif // V8_PPC_CONSTANTS_PPC_H_
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