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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1513543002: Add CMN instruction to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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201 201
202 void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 202 void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
203 bool SetFlags, CondARM32::Cond Cond); 203 bool SetFlags, CondARM32::Cond Cond);
204 204
205 void bl(const ConstantRelocatable *Target); 205 void bl(const ConstantRelocatable *Target);
206 206
207 void blx(const Operand *Target); 207 void blx(const Operand *Target);
208 208
209 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); 209 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
210 210
211 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
212
211 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); 213 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
212 214
213 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 215 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
214 bool SetFlags, CondARM32::Cond Cond); 216 bool SetFlags, CondARM32::Cond Cond);
215 217
216 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 218 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
217 const TargetInfo &TInfo); 219 const TargetInfo &TInfo);
218 220
219 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 221 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
220 const TargetLowering *Lowering) { 222 const TargetLowering *Lowering) {
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417 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and 419 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
418 // iiiiiiiiiiiiiiii=Imm16. 420 // iiiiiiiiiiiiiiii=Imm16.
419 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, 421 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
420 const Operand *OpSrc, const char *MovName); 422 const Operand *OpSrc, const char *MovName);
421 }; 423 };
422 424
423 } // end of namespace ARM32 425 } // end of namespace ARM32
424 } // end of namespace Ice 426 } // end of namespace Ice
425 427
426 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 428 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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