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| 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 
| 2 // | 2 // | 
| 3 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file | 
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a | 
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. | 
| 6 // | 6 // | 
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. | 
| 8 // | 8 // | 
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// | 
| 10 // | 10 // | 
| (...skipping 1023 matching lines...) Expand 10 before | Expand all | Expand 10 after  Loading... | 
| 1034   constexpr const char *BxName = "bx"; | 1034   constexpr const char *BxName = "bx"; | 
| 1035   verifyCondDefined(Cond, BxName); | 1035   verifyCondDefined(Cond, BxName); | 
| 1036   verifyRegDefined(Rm, "Rm", BxName); | 1036   verifyRegDefined(Rm, "Rm", BxName); | 
| 1037   AssemblerBuffer::EnsureCapacity ensured(&Buffer); | 1037   AssemblerBuffer::EnsureCapacity ensured(&Buffer); | 
| 1038   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | | 1038   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | | 
| 1039                            B21 | (0xfff << 8) | B4 | | 1039                            B21 | (0xfff << 8) | B4 | | 
| 1040                            (encodeGPRRegister(Rm) << kRmShift); | 1040                            (encodeGPRRegister(Rm) << kRmShift); | 
| 1041   emitInst(Encoding); | 1041   emitInst(Encoding); | 
| 1042 } | 1042 } | 
| 1043 | 1043 | 
|  | 1044 void AssemblerARM32::cmn(const Operand *OpRn, const Operand *OpSrc1, | 
|  | 1045                          CondARM32::Cond Cond) { | 
|  | 1046   // CMN (immediate) - ARM section A8.8.34, encoding A1: | 
|  | 1047   //   cmn<c> <Rn>, #<RotatedImm8> | 
|  | 1048   // | 
|  | 1049   // cccc00110111nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn, | 
|  | 1050   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8. | 
|  | 1051   // | 
|  | 1052   // CMN (register) - ARM section A8.8.35, encodeing A1: | 
|  | 1053   //   cmn<c> <Rn>, <Rm>{, <shift>} | 
|  | 1054   // | 
|  | 1055   // cccc00010111nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, | 
|  | 1056   // iiiii=Shift, and tt=ShiftKind. | 
|  | 1057   constexpr const char *CmnName = "cmn"; | 
|  | 1058   constexpr IValueT CmnOpcode = B3 | B1 | B0; // ie. 1011 | 
|  | 1059   emitCompareOp(Cond, CmnOpcode, OpRn, OpSrc1, CmnName); | 
|  | 1060 } | 
|  | 1061 | 
| 1044 void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1, | 1062 void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1, | 
| 1045                          CondARM32::Cond Cond) { | 1063                          CondARM32::Cond Cond) { | 
| 1046   // CMP (register) - ARM section A8.8.38, encoding A1: | 1064   // CMP (register) - ARM section A8.8.38, encoding A1: | 
| 1047   //   cmp<c> <Rn>, <Rm>{, <shift>} | 1065   //   cmp<c> <Rn>, <Rm>{, <shift>} | 
| 1048   // | 1066   // | 
| 1049   // cccc00010101nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, | 1067   // cccc00010101nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, | 
| 1050   // iiiii=Shift, and tt=ShiftKind. | 1068   // iiiii=Shift, and tt=ShiftKind. | 
| 1051   // | 1069   // | 
| 1052   // CMP (immediate) - ARM section A8.8.37 | 1070   // CMP (immediate) - ARM section A8.8.37 | 
| 1053   //  cmp<c: <Rn>, #<RotatedImm8> | 1071   //  cmp<c: <Rn>, #<RotatedImm8> | 
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| 1640 | 1658 | 
| 1641 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, | 1659 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, | 
| 1642                          CondARM32::Cond Cond) { | 1660                          CondARM32::Cond Cond) { | 
| 1643   constexpr const char *UxtName = "uxt"; | 1661   constexpr const char *UxtName = "uxt"; | 
| 1644   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; | 1662   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; | 
| 1645   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); | 1663   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); | 
| 1646 } | 1664 } | 
| 1647 | 1665 | 
| 1648 } // end of namespace ARM32 | 1666 } // end of namespace ARM32 | 
| 1649 } // end of namespace Ice | 1667 } // end of namespace Ice | 
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