[turbofan] Store nodes use only MachineRepresentation, not MachineType.

test/unittests/compiler/x64/instruction-selector-x64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 #include "src/compiler/node-matchers.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 108 matching lines @@
   EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
   EXPECT_EQ(2U, s[0]->InputCount());
   EXPECT_EQ(1U, s[0]->OutputCount());
 }
 
 
 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
   const MemoryAccess memacc = GetParam();
   StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
                   MachineType::Int32(), memacc.type);
-  m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2),
-          kNoWriteBarrier);
+  m.Store(memacc.type.representation(), m.Parameter(0), m.Parameter(1),
+          m.Parameter(2), kNoWriteBarrier);
   m.Return(m.Int32Constant(0));
   Stream s = m.Build();
   ASSERT_EQ(1U, s.size());
   EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
   EXPECT_EQ(3U, s[0]->InputCount());
   EXPECT_EQ(0U, s[0]->OutputCount());
 }
 
 
 INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
@@ skipping 1189 matching lines @@
   EXPECT_EQ(kX64Lzcnt32, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->InputCount());
   EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8