[turbofan] Store nodes use only MachineRepresentation, not MachineType.

test/unittests/compiler/ia32/instruction-selector-ia32-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 237 matching lines @@
     }
     EXPECT_EQ(1U, s[0]->OutputCount());
   }
 }
 
 
 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
   const MemoryAccess memacc = GetParam();
   StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
                   MachineType::Int32(), memacc.type);
-  m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2),
-          kNoWriteBarrier);
+  m.Store(memacc.type.representation(), m.Parameter(0), m.Parameter(1),
+          m.Parameter(2), kNoWriteBarrier);
   m.Return(m.Int32Constant(0));
   Stream s = m.Build();
   ASSERT_EQ(1U, s.size());
   EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
   EXPECT_EQ(3U, s[0]->InputCount());
   EXPECT_EQ(0U, s[0]->OutputCount());
 }
 
 
 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateBase) {
   const MemoryAccess memacc = GetParam();
   TRACED_FOREACH(int32_t, base, kImmediates) {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
                     memacc.type);
-    m.Store(memacc.type, m.Int32Constant(base), m.Parameter(0), m.Parameter(1),
-            kNoWriteBarrier);
+    m.Store(memacc.type.representation(), m.Int32Constant(base), m.Parameter(0),
+            m.Parameter(1), kNoWriteBarrier);
     m.Return(m.Int32Constant(0));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
     EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
     if (base == 0) {
       ASSERT_EQ(2U, s[0]->InputCount());
     } else {
       ASSERT_EQ(3U, s[0]->InputCount());
       ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
       EXPECT_EQ(base, s.ToInt32(s[0]->InputAt(1)));
     }
     EXPECT_EQ(0U, s[0]->OutputCount());
   }
 }
 
 
 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) {
   const MemoryAccess memacc = GetParam();
   TRACED_FOREACH(int32_t, index, kImmediates) {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
                     memacc.type);
-    m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1),
-            kNoWriteBarrier);
+    m.Store(memacc.type.representation(), m.Parameter(0),
+            m.Int32Constant(index), m.Parameter(1), kNoWriteBarrier);
     m.Return(m.Int32Constant(0));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
     EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
     if (index == 0) {
       ASSERT_EQ(2U, s[0]->InputCount());
     } else {
       ASSERT_EQ(3U, s[0]->InputCount());
       ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
       EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
@@ skipping 13 matching lines @@
 
 
 class AddressingModeUnitTest : public InstructionSelectorTest {
  public:
   AddressingModeUnitTest() : m(NULL) { Reset(); }
   ~AddressingModeUnitTest() { delete m; }
 
   void Run(Node* base, Node* load_index, Node* store_index,
            AddressingMode mode) {
     Node* load = m->Load(MachineType::Int32(), base, load_index);
-    m->Store(MachineType::Int32(), base, store_index, load, kNoWriteBarrier);
+    m->Store(MachineRepresentation::kWord32, base, store_index, load,
+             kNoWriteBarrier);
     m->Return(m->Int32Constant(0));
     Stream s = m->Build();
     ASSERT_EQ(2U, s.size());
     EXPECT_EQ(mode, s[0]->addressing_mode());
     EXPECT_EQ(mode, s[1]->addressing_mode());
   }
 
   Node* zero;
   Node* null_ptr;
   Node* non_zero;
@@ skipping 505 matching lines @@
   EXPECT_EQ(kIA32Lzcnt, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->InputCount());
   EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8