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| 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 1279 ++IntegerCount; | 1279 ++IntegerCount; |
| 1280 } | 1280 } |
| 1281 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); | 1281 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); |
| 1282 switch (IntegerCount) { | 1282 switch (IntegerCount) { |
| 1283 case 0: | 1283 case 0: |
| 1284 return; | 1284 return; |
| 1285 case 1: | 1285 case 1: |
| 1286 // Note: Can only apply pop register if single register is not sp. | 1286 // Note: Can only apply pop register if single register is not sp. |
| 1287 assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) && | 1287 assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) && |
| 1288 "Effects of pop register SP is undefined!"); | 1288 "Effects of pop register SP is undefined!"); |
| 1289 // TODO(kschimpf) ARM sandbox does not allow the single register form of | |
| 1290 // pop, and the popList form expects multiple registers. Convert this | |
| 1291 // assert to a conditional check once it has been shown that popList | |
| 1292 // works. | |
| 1293 assert(!Func->getContext()->getFlags().getUseSandboxing() && | |
| 1294 "pop register not in ARM sandbox!"); | |
| 1295 Asm->pop(LastDest, CondARM32::AL); | 1289 Asm->pop(LastDest, CondARM32::AL); |
| 1296 break; | 1290 break; |
| 1297 default: | 1291 default: |
| 1298 Asm->popList(GPRegisters, CondARM32::AL); | 1292 Asm->popList(GPRegisters, CondARM32::AL); |
| 1299 break; | 1293 break; |
| 1300 } | 1294 } |
| 1301 if (Asm->needsTextFixup()) | 1295 if (Asm->needsTextFixup()) |
| 1302 emitUsingTextFixup(Func); | 1296 emitUsingTextFixup(Func); |
| 1303 } | 1297 } |
| 1304 | 1298 |
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| 1385 ++IntegerCount; | 1379 ++IntegerCount; |
| 1386 } | 1380 } |
| 1387 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); | 1381 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); |
| 1388 switch (IntegerCount) { | 1382 switch (IntegerCount) { |
| 1389 case 0: | 1383 case 0: |
| 1390 return; | 1384 return; |
| 1391 case 1: { | 1385 case 1: { |
| 1392 // Note: Can only apply push register if single register is not sp. | 1386 // Note: Can only apply push register if single register is not sp. |
| 1393 assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) && | 1387 assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) && |
| 1394 "Effects of push register SP is undefined!"); | 1388 "Effects of push register SP is undefined!"); |
| 1395 // TODO(kschimpf) ARM sandbox does not allow the single register form of | |
| 1396 // push, and the pushList form expects multiple registers. Convert this | |
| 1397 // assert to a conditional check once it has been shown that pushList | |
| 1398 // works. | |
| 1399 assert(!Func->getContext()->getFlags().getUseSandboxing() && | |
| 1400 "push register not in ARM sandbox!"); | |
| 1401 Asm->push(LastSrc, CondARM32::AL); | 1389 Asm->push(LastSrc, CondARM32::AL); |
| 1402 break; | 1390 break; |
| 1403 } | 1391 } |
| 1404 default: | 1392 default: |
| 1405 // TODO(kschimpf) Implement pushList in assembler. | 1393 // TODO(kschimpf) Implement pushList in assembler. |
| 1406 Asm->pushList(GPRegisters, CondARM32::AL); | 1394 Asm->pushList(GPRegisters, CondARM32::AL); |
| 1407 break; | 1395 break; |
| 1408 } | 1396 } |
| 1409 if (Asm->needsTextFixup()) | 1397 if (Asm->needsTextFixup()) |
| 1410 emitUsingTextFixup(Func); | 1398 emitUsingTextFixup(Func); |
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| 1789 } | 1777 } |
| 1790 Str << "] AddrMode==" << getAddrMode(); | 1778 Str << "] AddrMode==" << getAddrMode(); |
| 1791 } | 1779 } |
| 1792 | 1780 |
| 1793 void OperandARM32ShAmtImm::emit(const Cfg *Func) const { ShAmt->emit(Func); } | 1781 void OperandARM32ShAmtImm::emit(const Cfg *Func) const { ShAmt->emit(Func); } |
| 1794 | 1782 |
| 1795 void OperandARM32ShAmtImm::dump(const Cfg *, Ostream &Str) const { | 1783 void OperandARM32ShAmtImm::dump(const Cfg *, Ostream &Str) const { |
| 1796 ShAmt->dump(Str); | 1784 ShAmt->dump(Str); |
| 1797 } | 1785 } |
| 1798 | 1786 |
| 1787 OperandARM32FlexImm *OperandARM32FlexImm::create(Cfg *Func, Type Ty, |
| 1788 uint32_t Imm, |
| 1789 uint32_t RotateAmt) { |
| 1790 // The assembler wants the smallest rotation. Rotate if needed. Note: Imm is |
| 1791 // an 8-bit value. |
| 1792 assert(Utils::IsUint(8, Imm) && |
| 1793 "Flex immediates can only be defined on 8-bit immediates"); |
| 1794 while ((Imm & 0x03) == 0 && RotateAmt > 0) { |
| 1795 --RotateAmt; |
| 1796 Imm = Imm >> 2; |
| 1797 } |
| 1798 return new (Func->allocate<OperandARM32FlexImm>()) |
| 1799 OperandARM32FlexImm(Func, Ty, Imm, RotateAmt); |
| 1800 } |
| 1801 |
| 1799 void OperandARM32FlexImm::emit(const Cfg *Func) const { | 1802 void OperandARM32FlexImm::emit(const Cfg *Func) const { |
| 1800 if (!BuildDefs::dump()) | 1803 if (!BuildDefs::dump()) |
| 1801 return; | 1804 return; |
| 1802 Ostream &Str = Func->getContext()->getStrEmit(); | 1805 Ostream &Str = Func->getContext()->getStrEmit(); |
| 1803 uint32_t Imm = getImm(); | 1806 uint32_t Imm = getImm(); |
| 1804 uint32_t RotateAmt = getRotateAmt(); | 1807 uint32_t RotateAmt = getRotateAmt(); |
| 1805 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt); | 1808 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt); |
| 1806 } | 1809 } |
| 1807 | 1810 |
| 1808 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const { | 1811 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const { |
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| 1941 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; | 1944 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; |
| 1942 | 1945 |
| 1943 template class InstARM32FourAddrGPR<InstARM32::Mla>; | 1946 template class InstARM32FourAddrGPR<InstARM32::Mla>; |
| 1944 template class InstARM32FourAddrGPR<InstARM32::Mls>; | 1947 template class InstARM32FourAddrGPR<InstARM32::Mls>; |
| 1945 | 1948 |
| 1946 template class InstARM32CmpLike<InstARM32::Cmn>; | 1949 template class InstARM32CmpLike<InstARM32::Cmn>; |
| 1947 template class InstARM32CmpLike<InstARM32::Cmp>; | 1950 template class InstARM32CmpLike<InstARM32::Cmp>; |
| 1948 template class InstARM32CmpLike<InstARM32::Tst>; | 1951 template class InstARM32CmpLike<InstARM32::Tst>; |
| 1949 | 1952 |
| 1950 } // end of namespace Ice | 1953 } // end of namespace Ice |
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