Fix problems with sandboxing and the ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 117 matching lines @@
 
   const char *getAlignDirective() const override { return ".p2alignl"; }
 
   llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override {
     // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0
     // http://llvm.org/viewvc/llvm-project?view=revision&revision=173943
     static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0};
     return llvm::ArrayRef<uint8_t>(Padding, 4);
   }
 
-  void padWithNop(intptr_t Padding) override {
-    (void)Padding;
-    llvm_unreachable("Not yet implemented.");
-  }
+  void padWithNop(intptr_t Padding) override;
 
   Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override {
     assert(NodeNumber < CfgNodeLabels.size());
     return CfgNodeLabels[NodeNumber];
   }
 
   Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
     return getOrCreateLabel(NodeNumber, CfgNodeLabels);
   }
 
@@ skipping 85 matching lines @@
   void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
            const Operand *OpRa, CondARM32::Cond Cond);
 
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond);
 
+  void nop();
+
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void pop(const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void popList(const IValueT Registers, CondARM32::Cond Cond);
 
   void push(const Operand *OpRt, CondARM32::Cond Cond);
 
@@ skipping 162 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H