Fix problems with sandboxing and the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 442 matching lines @@
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
       << "bl\t" << symbol(Ctx) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
+void AssemblerARM32::padWithNop(intptr_t Padding) {
+  constexpr intptr_t InstWidth = sizeof(IValueT);
+  assert(Padding % InstWidth == 0 &&
+         "Padding not multiple of instruction size");
+  for (intptr_t i = 0; i < Padding; i += InstWidth)
+    nop();
+}
+
 BlRelocatableFixup *
 AssemblerARM32::createBlFixup(const ConstantRelocatable *BlTarget) {
   BlRelocatableFixup *F =
       new (allocate<BlRelocatableFixup>()) BlRelocatableFixup();
   F->set_kind(llvm::ELF::R_ARM_CALL);
   F->set_value(BlTarget);
   Buffer.installFixup(F);
   return F;
 }
 
@@ skipping 171 matching lines @@
   // TODO(kschimpf): Handle far jumps.
   constexpr const char *BranchName = "b";
   if (L->isBound()) {
     const int32_t Dest = L->getPosition() - Buffer.size();
     emitType05(Cond, Dest, Link, BranchName);
     return;
   }
   const IOffsetT Position = Buffer.size();
   // Use the offset field of the branch instruction for linking the sites.
   emitType05(Cond, L->getEncodedPosition(), Link, BranchName);
-  if (!needsTextFixup())
-    L->linkTo(Position);
+  L->linkTo(*this, Position);
 }
 
 void AssemblerARM32::emitCompareOp(CondARM32::Cond Cond, IValueT Opcode,
                                    const Operand *OpRn, const Operand *OpSrc1,
                                    const char *InstName) {
   // XXX (register)
   //   XXX<c> <Rn>, <Rm>{, <shift>}
   //
   // ccccyyyxxxx1nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, iiiii
   // defines shift constant, tt=ShiftKind, yyy=kInstTypeDataRegister, and
@@ skipping 44 matching lines @@
 
     // Check if conditions of rules violated.
     verifyRegNotPc(Rn, "Rn", InstName);
     verifyPOrNotW(Address, InstName);
     if (!IsByte && (Rn == RegARM32::Encoded_Reg_sp) && !isBitSet(P, Address) &&
         isBitSet(U, Address) && !isBitSet(W, Address) &&
         (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
       llvm::report_fatal_error(std::string(InstName) +
                                ": Use push/pop instead");
 
-    return emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address,
-                     InstName);
+    emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address,
+              InstName);
+    return;
   }
   case EncodedAsShiftRotateImm5: {
     // XXX{B} (register)
     //   xxx{b}<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   xxx{b}<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
     //
     // cccc011pubwlnnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt,
     // b=IsByte, U=1 if +, pu0b is a BlockAddr, l=IsLoad, and
     // pu0w0nnnn0000iiiiiss0mmmm=Address.
     RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
     RegARM32::GPRRegister Rm = getGPRReg(kRmShift, Address);
 
     // Check if conditions of rules violated.
     verifyPOrNotW(Address, InstName);
     verifyRegNotPc(Rm, "Rm", InstName);
     if (IsByte)
       verifyRegNotPc(Rt, "Rt", InstName);
     if (isBitSet(W, Address)) {
       verifyRegNotPc(Rn, "Rn", InstName);
       verifyRegsNotEq(Rn, "Rn", Rt, "Rt", InstName);
     }
-    return emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address,
-                     InstName);
+    emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address,
+              InstName);
+    return;
   }
   }
 }
 
 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode,
                                    IValueT Rt, const Operand *OpAddress,
                                    const TargetInfo &TInfo,
                                    const char *InstName) {
   IValueT Address;
   switch (encodeAddress(OpAddress, Address, TInfo, OpEncoding3)) {
@@ skipping 11 matching lines @@
     // and pu0w0nnnn0000iiii0000jjjj=Address.
     verifyRegDefined(Rt, "Rt", InstName);
     verifyCondDefined(Cond, InstName);
     verifyPOrNotW(Address, InstName);
     verifyRegNotPc(Rt, "Rt", InstName);
     if (isBitSet(W, Address))
       verifyRegsNotEq(getGPRReg(kRnShift, Address), "Rn", Rt, "Rt", InstName);
     const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                              Opcode | (Rt << kRdShift) | Address;
     AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-    return emitInst(Encoding);
+    emitInst(Encoding);
+    return;
   }
   case EncodedAsShiftRotateImm5: {
     // XXXH (register)
     //   xxxh<c> <Rt>, [<Rn>, +/-<Rm>]{!}
     //   xxxh<c> <Rt>, [<Rn>], +/-<Rm>
     //
     // cccc000pu0wxnnnntttt00001011mmmm where cccc=Cond, tttt=Rt, nnnn=Rn,
     // mmmm=Rm, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode, and
     // pu0w0nnnn000000000000mmmm=Address.
     verifyRegDefined(Rt, "Rt", InstName);
     verifyCondDefined(Cond, InstName);
     verifyPOrNotW(Address, InstName);
     verifyRegNotPc(Rt, "Rt", InstName);
     verifyAddrRegNotPc(kRmShift, Address, "Rm", InstName);
     const RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
     if (isBitSet(W, Address)) {
       verifyRegNotPc(Rn, "Rn", InstName);
       verifyRegsNotEq(Rn, "Rn", Rt, "Rt", InstName);
     }
     if (mask(Address, kShiftImmShift, 5) != 0)
       // For encoding 3, no shift is allowed.
       llvm::report_fatal_error(std::string(InstName) +
                                ": Shift constant not allowed");
     const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                              Opcode | (Rt << kRdShift) | Address;
     AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-    return emitInst(Encoding);
+    emitInst(Encoding);
+    return;
   }
   }
 }
 
 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
                                IValueT Rn, IValueT Rm, const char *InstName) {
   verifyRegDefined(Rd, "Rd", InstName);
   verifyRegDefined(Rn, "Rn", InstName);
   verifyRegDefined(Rm, "Rm", InstName);
   verifyCondDefined(Cond, InstName);
@@ skipping 309 matching lines @@
     // iiiiiiiiiiii=imm12, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     //
     // LDRB (register) - ARM section A8.8.66, encoding A1:
     //   ldrb<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   ldrb<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
     //
     // cccc011pu1w1nnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt, U=1 if +, pu0b
     // is a BlockAddr, and pu0w0nnnn0000iiiiiss0mmmm=Address.
     constexpr bool IsByte = true;
-    return emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
+    emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
+    return;
   }
   case 1: {
     // Handles i16 loads.
     //
     // LDRH (immediate) - ARM section A8.8.80, encoding A1:
     //   ldrh<c> <Rt>, [<Rn>{, #+/-<Imm8>}]
     //   ldrh<c> <Rt>, [<Rn>], #+/-<Imm8>
     //   ldrh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu1w1nnnnttttiiii1011iiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiii=Imm8, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     constexpr const char *Ldrh = "ldrh";
-    return emitMemOpEnc3(Cond, L | B7 | B5 | B4, Rt, OpAddress, TInfo, Ldrh);
+    emitMemOpEnc3(Cond, L | B7 | B5 | B4, Rt, OpAddress, TInfo, Ldrh);
+    return;
   }
   case 2: {
     // Note: Handles i32 and float loads. Target lowering handles i64 and
     // double by using two (32 bit) load instructions.
     //
     // LDR (immediate) - ARM section A8.8.63, encoding A1:
     //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
     //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
     //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
     //
     // cccc010pu0w1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +, pu0w is a BlockAddr, and
     //
     // LDR (register) - ARM section A8.8.70, encoding A1:
     //   ldrb<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   ldrb<c> <Rt>, [<Rn>], +-<Rm>{, <shift>}
     //
     // cccc011pu0w1nnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt, U=1 if +, pu0b
     // is a BlockAddr, and pu0w0nnnn0000iiiiiss0mmmm=Address.
     constexpr bool IsByte = false;
-    return emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
+    emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName);
+    return;
   }
   }
 }
 
 void AssemblerARM32::emitShift(const CondARM32::Cond Cond,
                                const OperandARM32::ShiftKind Shift,
                                const Operand *OpRd, const Operand *OpRm,
                                const Operand *OpSrc1, const bool SetFlags,
                                const char *InstName) {
   constexpr IValueT ShiftOpcode = B3 | B2 | B0; // 1101
@@ skipping 141 matching lines @@
   // mmmm=Rm, iiii defines shift constant, and tt=ShiftKind.
   constexpr const char *MvnName = "mvn";
   IValueT Rd = encodeRegister(OpRd, "Rd", MvnName);
   constexpr IValueT MvnOpcode = B3 | B2 | B1 | B0; // i.e. 1111
   constexpr IValueT Rn = 0;
   constexpr bool SetFlags = false;
   emitType01(Cond, MvnOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags,
              MvnName);
 }
 
+void AssemblerARM32::nop() {
+  // NOP - Section A8.8.119, encoding A1:
+  //  nop<c>
+  //
+  // cccc0011001000001111000000000000 where cccc=Cond.
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr CondARM32::Cond Cond = CondARM32::AL;
+  const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 |
+                           B24 | B21 | B15 | B14 | B13 | B12;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SBC (register) - ARM section 18.8.162, encoding A1:
   //   sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // SBC (Immediate) - ARM section A8.8.161, encoding A1:
@@ skipping 44 matching lines @@
     // Handles i1 and i8 stores.
     //
     // STRB (immediate) - ARM section A8.8.207, encoding A1:
     //   strb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
     //   strb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
     //   strb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
     //
     // cccc010pu1w0nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +.
     constexpr bool IsByte = true;
-    return emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
+    emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
+    return;
   }
   case 1: {
     // Handles i16 stores.
     //
     // STRH (immediate) - ARM section A8.*.217, encoding A1:
     //   strh<c> <Rt>, [<Rn>{, #+/-<Imm8>}]
     //   strh<c> <Rt>, [<Rn>], #+/-<Imm8>
     //   strh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu1w0nnnnttttiiii1011iiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiii=Imm8, u=1 if +, pu0w is a BlockAddr, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     constexpr const char *Strh = "strh";
-    return emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh);
+    emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh);
+    return;
   }
   case 2: {
     // Note: Handles i32 and float stores. Target lowering handles i64 and
     // double by using two (32 bit) store instructions.
     //
     // STR (immediate) - ARM section A8.8.207, encoding A1:
     //   str<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
     //   str<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
     //   str<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
     //
     // cccc010pu1w0nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, u=1 if +.
     constexpr bool IsByte = false;
-    return emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
-    return setNeedsTextFixup();
+    emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName);
+    return;
   }
   }
 }
 
 void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ORR (register) - ARM Section A8.8.123, encoding A1:
   //   orr{s}<c> <Rd>, <Rn>, <Rm>
   //
@@ skipping 224 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice