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Side by Side Diff: src/IceInstARM32.cpp

Issue 1511653002: Fix problems with sandboxing and the ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years ago
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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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1256 ++IntegerCount; 1256 ++IntegerCount;
1257 } 1257 }
1258 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); 1258 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
1259 switch (IntegerCount) { 1259 switch (IntegerCount) {
1260 case 0: 1260 case 0:
1261 return; 1261 return;
1262 case 1: 1262 case 1:
1263 // Note: Can only apply pop register if single register is not sp. 1263 // Note: Can only apply pop register if single register is not sp.
1264 assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) && 1264 assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) &&
1265 "Effects of pop register SP is undefined!"); 1265 "Effects of pop register SP is undefined!");
1266 // TODO(kschimpf) ARM sandbox does not allow the single register form of
1267 // pop, and the popList form expects multiple registers. Convert this
1268 // assert to a conditional check once it has been shown that popList
1269 // works.
1270 assert(!Func->getContext()->getFlags().getUseSandboxing() &&
1271 "pop register not in ARM sandbox!");
1272 Asm->pop(LastDest, CondARM32::AL); 1266 Asm->pop(LastDest, CondARM32::AL);
1273 break; 1267 break;
1274 default: 1268 default:
1275 Asm->popList(GPRegisters, CondARM32::AL); 1269 Asm->popList(GPRegisters, CondARM32::AL);
1276 break; 1270 break;
1277 } 1271 }
1278 if (Asm->needsTextFixup()) 1272 if (Asm->needsTextFixup())
1279 emitUsingTextFixup(Func); 1273 emitUsingTextFixup(Func);
1280 } 1274 }
1281 1275
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1362 ++IntegerCount; 1356 ++IntegerCount;
1363 } 1357 }
1364 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); 1358 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
1365 switch (IntegerCount) { 1359 switch (IntegerCount) {
1366 case 0: 1360 case 0:
1367 return; 1361 return;
1368 case 1: { 1362 case 1: {
1369 // Note: Can only apply push register if single register is not sp. 1363 // Note: Can only apply push register if single register is not sp.
1370 assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) && 1364 assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) &&
1371 "Effects of push register SP is undefined!"); 1365 "Effects of push register SP is undefined!");
1372 // TODO(kschimpf) ARM sandbox does not allow the single register form of
1373 // push, and the pushList form expects multiple registers. Convert this
1374 // assert to a conditional check once it has been shown that pushList
1375 // works.
1376 assert(!Func->getContext()->getFlags().getUseSandboxing() &&
1377 "push register not in ARM sandbox!");
1378 Asm->push(LastSrc, CondARM32::AL); 1366 Asm->push(LastSrc, CondARM32::AL);
1379 break; 1367 break;
1380 } 1368 }
1381 default: 1369 default:
1382 // TODO(kschimpf) Implement pushList in assembler. 1370 // TODO(kschimpf) Implement pushList in assembler.
1383 Asm->pushList(GPRegisters, CondARM32::AL); 1371 Asm->pushList(GPRegisters, CondARM32::AL);
1384 break; 1372 break;
1385 } 1373 }
1386 if (Asm->needsTextFixup()) 1374 if (Asm->needsTextFixup())
1387 emitUsingTextFixup(Func); 1375 emitUsingTextFixup(Func);
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1766 } 1754 }
1767 Str << "] AddrMode==" << getAddrMode(); 1755 Str << "] AddrMode==" << getAddrMode();
1768 } 1756 }
1769 1757
1770 void OperandARM32ShAmtImm::emit(const Cfg *Func) const { ShAmt->emit(Func); } 1758 void OperandARM32ShAmtImm::emit(const Cfg *Func) const { ShAmt->emit(Func); }
1771 1759
1772 void OperandARM32ShAmtImm::dump(const Cfg *, Ostream &Str) const { 1760 void OperandARM32ShAmtImm::dump(const Cfg *, Ostream &Str) const {
1773 ShAmt->dump(Str); 1761 ShAmt->dump(Str);
1774 } 1762 }
1775 1763
1764 OperandARM32FlexImm *OperandARM32FlexImm::create(Cfg *Func, Type Ty,
1765 uint32_t Imm,
1766 uint32_t RotateAmt) {
1767 // The assembler wants the smallest rotation. Rotate if needed. Note: Imm is
John 2015/12/08 19:45:04 Why is this needed?
Karl 2015/12/08 19:58:35 If I don't do this, then values like rotate=2, Imm
1768 // an 8-bit value.
Jim Stichnoth 2015/12/08 19:54:58 Maybe validate Imm? e.g. assert(Utils::IsUint(8
Karl 2015/12/08 20:49:36 Added assert.
1769 while ((Imm & 0x03) == 0 && RotateAmt > 0) {
1770 --RotateAmt;
1771 Imm = Imm >> 2;
1772 }
1773 return new (Func->allocate<OperandARM32FlexImm>())
1774 OperandARM32FlexImm(Func, Ty, Imm, RotateAmt);
1775 }
1776
1776 void OperandARM32FlexImm::emit(const Cfg *Func) const { 1777 void OperandARM32FlexImm::emit(const Cfg *Func) const {
1777 if (!BuildDefs::dump()) 1778 if (!BuildDefs::dump())
1778 return; 1779 return;
1779 Ostream &Str = Func->getContext()->getStrEmit(); 1780 Ostream &Str = Func->getContext()->getStrEmit();
1780 uint32_t Imm = getImm(); 1781 uint32_t Imm = getImm();
1781 uint32_t RotateAmt = getRotateAmt(); 1782 uint32_t RotateAmt = getRotateAmt();
1782 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt); 1783 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt);
1783 } 1784 }
1784 1785
1785 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const { 1786 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const {
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1918 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; 1919 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
1919 1920
1920 template class InstARM32FourAddrGPR<InstARM32::Mla>; 1921 template class InstARM32FourAddrGPR<InstARM32::Mla>;
1921 template class InstARM32FourAddrGPR<InstARM32::Mls>; 1922 template class InstARM32FourAddrGPR<InstARM32::Mls>;
1922 1923
1923 template class InstARM32CmpLike<InstARM32::Cmn>; 1924 template class InstARM32CmpLike<InstARM32::Cmn>;
1924 template class InstARM32CmpLike<InstARM32::Cmp>; 1925 template class InstARM32CmpLike<InstARM32::Cmp>;
1925 template class InstARM32CmpLike<InstARM32::Tst>; 1926 template class InstARM32CmpLike<InstARM32::Tst>;
1926 1927
1927 } // end of namespace Ice 1928 } // end of namespace Ice
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