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| 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
| 6 // | 6 // |
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
| 8 // | 8 // |
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
| 10 // | 10 // |
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| 128 | 128 |
| 129 const char *getAlignDirective() const override { return ".p2alignl"; } | 129 const char *getAlignDirective() const override { return ".p2alignl"; } |
| 130 | 130 |
| 131 llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override { | 131 llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override { |
| 132 // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0 | 132 // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0 |
| 133 // http://llvm.org/viewvc/llvm-project?view=revision&revision=173943 | 133 // http://llvm.org/viewvc/llvm-project?view=revision&revision=173943 |
| 134 static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0}; | 134 static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0}; |
| 135 return llvm::ArrayRef<uint8_t>(Padding, 4); | 135 return llvm::ArrayRef<uint8_t>(Padding, 4); |
| 136 } | 136 } |
| 137 | 137 |
| 138 void padWithNop(intptr_t Padding) override { | 138 void padWithNop(intptr_t Padding) override; |
| 139 (void)Padding; | |
| 140 llvm_unreachable("Not yet implemented."); | |
| 141 } | |
| 142 | 139 |
| 143 Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override { | 140 Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override { |
| 144 assert(NodeNumber < CfgNodeLabels.size()); | 141 assert(NodeNumber < CfgNodeLabels.size()); |
| 145 return CfgNodeLabels[NodeNumber]; | 142 return CfgNodeLabels[NodeNumber]; |
| 146 } | 143 } |
| 147 | 144 |
| 148 Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) { | 145 Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) { |
| 149 return getOrCreateLabel(NodeNumber, CfgNodeLabels); | 146 return getOrCreateLabel(NodeNumber, CfgNodeLabels); |
| 150 } | 147 } |
| 151 | 148 |
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| 232 void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); | 229 void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
| 233 | 230 |
| 234 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, | 231 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, |
| 235 const Operand *OpRa, CondARM32::Cond Cond); | 232 const Operand *OpRa, CondARM32::Cond Cond); |
| 236 | 233 |
| 237 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 234 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 238 bool SetFlags, CondARM32::Cond Cond); | 235 bool SetFlags, CondARM32::Cond Cond); |
| 239 | 236 |
| 240 void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond); | 237 void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond); |
| 241 | 238 |
| 239 void nop(const CondARM32::Cond = CondARM32::AL); | |
|
Jim Stichnoth
2015/12/08 19:54:58
Does nop *really* need to be predicated?
Karl
2015/12/08 20:49:36
Was following DART code. However, I agree that I c
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| 240 | |
| 242 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 241 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 243 bool SetFlags, CondARM32::Cond Cond); | 242 bool SetFlags, CondARM32::Cond Cond); |
| 244 | 243 |
| 245 void pop(const Operand *OpRt, CondARM32::Cond Cond); | 244 void pop(const Operand *OpRt, CondARM32::Cond Cond); |
| 246 | 245 |
| 247 // Note: Registers is a bitset, where bit n corresponds to register Rn. | 246 // Note: Registers is a bitset, where bit n corresponds to register Rn. |
| 248 void popList(const IValueT Registers, CondARM32::Cond Cond); | 247 void popList(const IValueT Registers, CondARM32::Cond Cond); |
| 249 | 248 |
| 250 void push(const Operand *OpRt, CondARM32::Cond Cond); | 249 void push(const Operand *OpRt, CondARM32::Cond Cond); |
| 251 | 250 |
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| 411 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and | 410 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and |
| 412 // iiiiiiiiiiiiiiii=Imm16. | 411 // iiiiiiiiiiiiiiii=Imm16. |
| 413 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, | 412 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, |
| 414 const Operand *OpSrc, const char *MovName); | 413 const Operand *OpSrc, const char *MovName); |
| 415 }; | 414 }; |
| 416 | 415 |
| 417 } // end of namespace ARM32 | 416 } // end of namespace ARM32 |
| 418 } // end of namespace Ice | 417 } // end of namespace Ice |
| 419 | 418 |
| 420 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 419 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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