A64: Synchronize with r16356.

src/ia32/disasm-ia32.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 588 matching lines @@
     if (op == 0xD1) {
       imm8 = 1;
     } else if (op == 0xC1) {
       imm8 = *(data+2);
       num_bytes = 3;
     } else if (op == 0xD3) {
       // Shift/rotate by cl.
     }
     ASSERT_NE(NULL, mnem);
     AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
-    if (imm8 > 0) {
+    if (imm8 >= 0) {
       AppendToBuffer("%d", imm8);
     } else {
       AppendToBuffer("cl");
     }
   } else {
     UnimplementedInstruction();
   }
   return num_bytes;
 }
 
@@ skipping 235 matching lines @@
   return 2;
 }
 
 
 // Mnemonics for instructions 0xF0 byte.
 // Returns NULL if the instruction is not handled here.
 static const char* F0Mnem(byte f0byte) {
   switch (f0byte) {
     case 0x18: return "prefetch";
     case 0xA2: return "cpuid";
-    case 0x31: return "rdtsc";
     case 0xBE: return "movsx_b";
     case 0xBF: return "movsx_w";
     case 0xB6: return "movzx_b";
     case 0xB7: return "movzx_w";
     case 0xAF: return "imul";
     case 0xA5: return "shld";
     case 0xAD: return "shrd";
     case 0xAC: return "shrd";  // 3-operand version.
     case 0xAB: return "bts";
     default: return NULL;
@@ skipping 842 matching lines @@
       fprintf(f, "  ");
     }
     fprintf(f, "  %s\n", buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_IA32