A64: Synchronize with r16356.

src/a64/cpu-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 120 matching lines @@
       [isize] "r"  (isize),
       [end]   "r"  (end)
     // This code does not write to memory but without the dependency gcc might
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif
 }
 
 
-void CPU::DebugBreak() {
-#if defined(USE_SIMULATOR)
-  asm volatile("int $3");
-#else
-  asm volatile("hlt 0");
-#endif
-}
-
-
 void CpuFeatures::Probe() {
   // Compute I and D cache line size. The cache type register holds
   // information about the caches.
   uint32_t cache_type_register = GetCacheType();
 
   static const int kDCacheLineSizeShift = 16;
   static const int kICacheLineSizeShift = 0;
   static const uint32_t kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift;
   static const uint32_t kICacheLineSizeMask = 0xf << kICacheLineSizeShift;
 
@@ skipping 38 matching lines @@
   // Copy the content of the cache type register to a core register.
   __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
                         : [ctr] "=r" (cache_type_register));
   return cache_type_register;
 #endif
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64