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Issue 1511223002: MIPS: [turbofan] Fix Div operations by zero on r6. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/ast/scopes.h" 5 #include "src/ast/scopes.h"
6 #include "src/compiler/code-generator.h" 6 #include "src/compiler/code-generator.h"
7 #include "src/compiler/code-generator-impl.h" 7 #include "src/compiler/code-generator-impl.h"
8 #include "src/compiler/gap-resolver.h" 8 #include "src/compiler/gap-resolver.h"
9 #include "src/compiler/node-matchers.h" 9 #include "src/compiler/node-matchers.h"
10 #include "src/compiler/osr.h" 10 #include "src/compiler/osr.h"
(...skipping 631 matching lines...) Expand 10 before | Expand all | Expand 10 after
642 break; 642 break;
643 case kMips64MulHighU: 643 case kMips64MulHighU:
644 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 644 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
645 break; 645 break;
646 case kMips64DMulHigh: 646 case kMips64DMulHigh:
647 __ Dmulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 647 __ Dmulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
648 break; 648 break;
649 case kMips64Div: 649 case kMips64Div:
650 __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 650 __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
651 if (kArchVariant == kMips64r6) { 651 if (kArchVariant == kMips64r6) {
652 __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0)); 652 __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
653 } else { 653 } else {
654 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1)); 654 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
655 } 655 }
656 break; 656 break;
657 case kMips64DivU: 657 case kMips64DivU:
658 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 658 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
659 if (kArchVariant == kMips64r6) { 659 if (kArchVariant == kMips64r6) {
660 __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0)); 660 __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
661 } else { 661 } else {
662 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1)); 662 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
663 } 663 }
664 break; 664 break;
665 case kMips64Mod: 665 case kMips64Mod:
666 __ Mod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 666 __ Mod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
667 break; 667 break;
668 case kMips64ModU: 668 case kMips64ModU:
669 __ Modu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 669 __ Modu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
670 break; 670 break;
671 case kMips64Dmul: 671 case kMips64Dmul:
672 __ Dmul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 672 __ Dmul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
673 break; 673 break;
674 case kMips64Ddiv: 674 case kMips64Ddiv:
675 __ Ddiv(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 675 __ Ddiv(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
676 if (kArchVariant == kMips64r6) { 676 if (kArchVariant == kMips64r6) {
677 __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0)); 677 __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
678 } else { 678 } else {
679 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1)); 679 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
680 } 680 }
681 break; 681 break;
682 case kMips64DdivU: 682 case kMips64DdivU:
683 __ Ddivu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 683 __ Ddivu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
684 if (kArchVariant == kMips64r6) { 684 if (kArchVariant == kMips64r6) {
685 __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0)); 685 __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
686 } else { 686 } else {
687 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1)); 687 __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
688 } 688 }
689 break; 689 break;
690 case kMips64Dmod: 690 case kMips64Dmod:
691 __ Dmod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 691 __ Dmod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
692 break; 692 break;
693 case kMips64DmodU: 693 case kMips64DmodU:
694 __ Dmodu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 694 __ Dmodu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
695 break; 695 break;
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1850 padding_size -= v8::internal::Assembler::kInstrSize; 1850 padding_size -= v8::internal::Assembler::kInstrSize;
1851 } 1851 }
1852 } 1852 }
1853 } 1853 }
1854 1854
1855 #undef __ 1855 #undef __
1856 1856
1857 } // namespace compiler 1857 } // namespace compiler
1858 } // namespace internal 1858 } // namespace internal
1859 } // namespace v8 1859 } // namespace v8
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